invert numbering on CR HDLState.get_crregs

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index ce9b8309a6d62b9061f238678d9403b3f6d1c7df..4c79cd31a22fb431f6f9f5971466b126cd4e9d0b 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -72,7 +72,7 @@ LOG_LENGTH = 0    # Non-zero to enable log data collection
 # BRAM organisation: We never access more than
 #     -- WB_DATA_BITS at a time so to save
 #     -- resources we make the array only that wide, and
-#     -- use consecutive indices for to make a cache "line"
+#     -- use consecutive indices to make a cache "line"
 #     --
 #     -- ROW_SIZE is the width in bytes of the BRAM
 #     -- (based on WB, so 64-bits)

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index d2f4b51ff74b865c0e758c34e49db1f92f094634..4fd1ab3b7f0e5dd4fa9fe1461ef907a9cb20701d 100644 (file)
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -32,7 +32,7 @@ class HDLState(State):
     def get_crregs(self):
         self.crregs = []
         for i in range(8):
-            rval = yield self.core.regs.cr.regs[i].reg
+            rval = yield self.core.regs.cr.regs[7-i].reg
             self.crregs.append(rval)
         log("class hdl cr regs", list(map(hex, self.crregs)))