Remove cloneTypes in favor of autoclonetype

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index f5098cf384d69259089ccdb9dfee6a0cc6e4c3e7..ce1089a28d6e27b2cd26a4d946ee83a88b3c3afc 100644 (file)
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -8,7 +8,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
+import freechips.rocketchip.util.AsyncResetRegVec
 
 case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
 
@@ -75,7 +75,7 @@ object BasePinToIOF {
 // level, and we have to do the pinmux
 // outside of RocketChipTop.
 
-class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
+class GPIOPortIO(val c: GPIOParams) extends Bundle {
   val pins = Vec(c.width, new EnhancedPin())
   val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
   val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None

diff --git a/src/main/scala/devices/gpio/GPIOPins.scala b/src/main/scala/devices/gpio/GPIOPins.scala
index 85729237f6e9eac42a10190addfd19b481d52045..2cae881931cd4c6ef5b40030e88706ce75afde29 100644 (file)
--- a/src/main/scala/devices/gpio/GPIOPins.scala
+++ b/src/main/scala/devices/gpio/GPIOPins.scala
@@ -9,17 +9,11 @@ import sifive.blocks.devices.pinctrl.{Pin}
 // even though it looks like something that more directly talks to
 // a pin. It also makes it possible to change the exact
 // type of pad this connects to.
-class GPIOSignals[T <: Data] (pingen: ()=> T,  c: GPIOParams) extends Bundle {
+class GPIOSignals[T <: Data](private val pingen: ()=> T, val c: GPIOParams) extends Bundle {
   val pins = Vec(c.width, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 }
 
-class GPIOPins[T <: Pin] (pingen: ()=> T,  c: GPIOParams) extends GPIOSignals[T](pingen, c) {
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-}
+class GPIOPins[T <: Pin](pingen: ()=> T, c: GPIOParams) extends GPIOSignals[T](pingen, c)
 
 object GPIOPinsFromPort {
 

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index a4016f3c71a2fdca986a996c124826144c0b8480..32cf50df57ee38644bc9d96bc52db3d159958b4d 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -6,13 +6,9 @@ import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 
-class I2CSignals[T <: Data](pingen: () => T) extends Bundle {
-
+class I2CSignals[T <: Data](private val pingen: () => T) extends Bundle {
   val scl: T = pingen()
   val sda: T = pingen()
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 }
 
 class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen)

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index e098258c353ca682a4d2099c6521eac9f57c13e2..cc2c6edadf5baa34181d30a3ec42747fb6186f07 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -10,7 +10,6 @@ import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
-  override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
 

diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala
index aa7e032694d4aaf76ddf100a6264fbe86a2f8a30..2a9716beadb33983427fa9530782e1b9b5a620c8 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPins.scala
+++ b/src/main/scala/devices/pwm/PWMPins.scala
@@ -4,15 +4,11 @@ package sifive.blocks.devices.pwm
 import Chisel._
 import sifive.blocks.devices.pinctrl.{Pin}
 
-class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
-
+class PWMSignals[T <: Data](private val pingen: () => T, val c: PWMParams) extends Bundle {
   val pwm: Vec[T] = Vec(c.ncmp, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 }
 
-class PWMPins[T <: Pin] (pingen: ()=> T, c: PWMParams) extends PWMSignals[T](pingen, c)
+class PWMPins[T <: Pin](pingen: () => T, c: PWMParams) extends PWMSignals[T](pingen, c)
 
 object PWMPinsFromPort {
   def apply[T <: Pin] (pins: PWMSignals[T], port: PWMPortIO): Unit = {

diff --git a/src/main/scala/devices/spi/SPIBundle.scala b/src/main/scala/devices/spi/SPIBundle.scala
index 332edff9ef20cfed280a83c32481230f681c305f..aaef313673d890ef6496af2e270454b6b99c1aee 100644 (file)
--- a/src/main/scala/devices/spi/SPIBundle.scala
+++ b/src/main/scala/devices/spi/SPIBundle.scala
@@ -2,12 +2,8 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import freechips.rocketchip.util.GenericParameterizedBundle
 
-abstract class SPIBundle(val c: SPIParamsBase) extends GenericParameterizedBundle(c) {
-  override def cloneType: SPIBundle.this.type =
-    this.getClass.getConstructors.head.newInstance(c).asInstanceOf[this.type]
-}
+abstract class SPIBundle(val c: SPIParamsBase) extends Bundle
 
 class SPIDataIO extends Bundle {
   val i = Bool(INPUT)

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index e380bf90626276fdab006a9542a943e0acd362ca..bad0e6f8964f7610e67f3efd1db40a81db65a948 100644 (file)
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -5,15 +5,11 @@ import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
-class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
+class SPISignals[T <: Data](val pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
 
   val sck = pingen()
   val dq  = Vec(4, pingen())
   val cs  = Vec(c.csWidth, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-
 }
 
 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c)

diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala
index aeb3632cbf73acad9e1b49acb6a6884627113b6c..88fa34c781860f0154e9982035efa4f2b10089b4 100644 (file)
--- a/src/main/scala/devices/uart/UARTPins.scala
+++ b/src/main/scala/devices/uart/UARTPins.scala
@@ -6,15 +6,12 @@ import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin}
 
-class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {
+class UARTSignals[T <: Data](private val pingen: () => T) extends Bundle {
   val rxd = pingen()
   val txd = pingen()
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 }
 
-class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen)
+class UARTPins[T <: Pin](pingen: () => T) extends UARTSignals[T](pingen)
 
 object UARTPinsFromPort {
   def apply[T <: Pin](pins: UARTSignals[T], uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {

diff --git a/src/main/scala/util/Timer.scala b/src/main/scala/util/Timer.scala
index c46d2bef07ff68f6c677175be6f2b2b94ff07a5e..cc9c85d5923881b9eaebd5c6116612aa852e1dde 100644 (file)
--- a/src/main/scala/util/Timer.scala
+++ b/src/main/scala/util/Timer.scala
@@ -6,12 +6,10 @@ import Chisel.ImplicitConversions._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.util.WideCounter
 
-class SlaveRegIF(w: Int) extends Bundle {
+class SlaveRegIF(val w: Int) extends Bundle {
   val write = Valid(UInt(width = w)).flip
   val read = UInt(OUTPUT, w)
 
-  override def cloneType: this.type = new SlaveRegIF(w).asInstanceOf[this.type]
-
   def toRegField(dummy: Int = 0): RegField = {
     def writeFn(valid: Bool, data: UInt): Bool = {
       write.valid := valid