remove Logical operations from ALU pipeline

diff --git a/src/soc/alu/formal/proof_main_stage.py b/src/soc/alu/formal/proof_main_stage.py
index e25b1c51fe851bba81b23217a525f998e40dd6cd..f102fc2b1726ed4d87b9a7415f09b9c7c9438423 100644 (file)
--- a/src/soc/alu/formal/proof_main_stage.py
+++ b/src/soc/alu/formal/proof_main_stage.py
@@ -68,12 +68,6 @@ class Driver(Elaboratable):
         with m.Switch(rec.insn_type):
             with m.Case(InternalOp.OP_ADD):
                 comb += Assert(Cat(o, carry_out) == (a + b + carry_in))
-            with m.Case(InternalOp.OP_AND):
-                comb += Assert(dut.o.o == a & b)
-            with m.Case(InternalOp.OP_OR):
-                comb += Assert(dut.o.o == a | b)
-            with m.Case(InternalOp.OP_XOR):
-                comb += Assert(dut.o.o == a ^ b)
 
         return m
 

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index f5347d3fdfa88d25e3e456dc8ecf13c02dafb292..a89c2333aeea72c1b8be4839ed3828f00afafb48 100644 (file)
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -50,18 +50,6 @@ class ALUMainStage(PipeModBase):
                 comb += self.o.o.eq(add_output[1:-1])
                 comb += self.o.carry_out.eq(add_output[-1])
 
-            #### and ####
-            with m.Case(InternalOp.OP_AND):
-                comb += self.o.o.eq(self.i.a & self.i.b)
-
-            #### or ####
-            with m.Case(InternalOp.OP_OR):
-                comb += self.o.o.eq(self.i.a | self.i.b)
-
-            #### xor ####
-            with m.Case(InternalOp.OP_XOR):
-                comb += self.o.o.eq(self.i.a ^ self.i.b)
-
             #### exts (sign-extend) ####
             with m.Case(InternalOp.OP_EXTS):
                 with m.If(self.i.ctx.op.data_len == 1):

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index 604b5af28e4f10467a58a86af799cbd7e1c9ca0c..c7afb9a634d96dd7f68a557ef33ce886e061aab1 100644 (file)
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -102,7 +102,7 @@ class ALUTestCase(FHDLTestCase):
         test_data.append(tc)
 
     def test_rand(self):
-        insns = ["add", "add.", "and", "or", "xor", "subf"]
+        insns = ["add", "add.", "subf"]
         for i in range(40):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1, 2"]
@@ -122,17 +122,6 @@ class ALUTestCase(FHDLTestCase):
             initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
-    def test_rand_imm_logical(self):
-        insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
-        for i in range(10):
-            choice = random.choice(insns)
-            imm = random.randint(0, (1<<16)-1)
-            lst = [f"{choice} 3, 1, {imm}"]
-            print(lst)
-            initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
-        
     def test_adde(self):
         lst = ["adde. 5, 6, 7"]
         initial_regs = [0] * 32