def __init__(self):
super().__init__(64, 32)
self.w_ports = {'o': self.write_port("dest1"),
- 'o1': self.write_port("dest2")} # for now (LD/ST update)
+ #'o1': self.write_port("dest2") # for now (LD/ST update)
+ }
self.r_ports = {'ra': self.read_port("src1"),
'rbc': self.read_port("src3"),
'dmi': self.read_port("dmi")} # needed for Debug (DMI)
def __init__(self):
super().__init__(64, 5)
self.w_ports = {'fast1': self.write_port("dest3"),
- 'fast2': self.write_port("dest4"),
}
self.r_ports = {'fast1': self.read_port("src1"),
}
for regfile, spec in byregfiles_wr.items():
fuspecs = byregfiles_wrspec[regfile]
wrpickers[regfile] = {}
+
+ # argh, more port-merging
+ if regfile == 'INT':
+ fuspecs['o'] = [fuspecs.pop('o')]
+ fuspecs['o'].append(fuspecs.pop('o1'))
+ if regfile == 'FAST':
+ fuspecs['fast1'] = [fuspecs.pop('fast1')]
+ fuspecs['fast1'].append(fuspecs.pop('fast2'))
+
for (regname, fspec) in sort_fuspecs(fuspecs):
self.connect_wrport(m, fu_bitdict, wrpickers,
regfile, regname, fspec)