try different clock for sdr

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index ce6ba4364e43fd3492b531e64389c13434afa2fa..308da1b25c8de40a3676976b4415da725be67c0f 100644 (file)
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -19,10 +19,10 @@ class sdram(PBase):
                 "Ifc_sdram_out sdr{0}_out;".format(count)
 
     def get_clk_spc(self, typ):
-        return "clk0, slow_reset"
+        return "core_clock, core_reset"
 
     def get_clock_reset(self, name, count):
-        return "slow_clock, slow_reset"
+        return "clk0, core_reset"
 
     def mkfast_peripheral(self):
         return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"