still investigating

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 28c6b4d3c1edf14e22309c1dac49bac6e3d1bd05..8b05976f0d31b674f37596c972e6ef87d6186d9e 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -92,6 +92,7 @@ class ALUMainStage(PipeModBase):
                 comb += src1.eq(a[0:8])
                 for i in range(8):
                     comb += eqs[i].eq(src1 == b[8*i:8*(i+1)])
+                comb += o.data[0].eq(eqs.any())
                 comb += cr0.data.eq(Cat(Const(0, 2), eqs.any(), Const(0, 1)))
                 comb += cr0.ok.eq(1)
 

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index a98d3440905ddec7efd6c4d233172f19b0a24785..56a8770a8ef500a4a997903aadfc1ed71189206c 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -147,7 +147,7 @@ class ALUTestCase(FHDLTestCase):
             self.run_tst_program(Program(lst), initial_regs)
 
     def test_cmpeqb(self):
-        lst = ["cmpeqb cr0, 1, 2"]
+        lst = ["cmpeqb cr1, 1, 2"]
         for i in range(20):
             initial_regs = [0] * 32
             initial_regs[1] = i