wishbone: fix SRAM; improve tests for Decoder & Arbiter

diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index 3afc57df26a8adc9ee2b697d3ade4a7a27e9fa73..63d410950403dbbbd9060067fa712dffacf70a04 100644 (file)
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -137,10 +137,12 @@ class DecoderSimulationTestCase(unittest.TestCase):
         dut = Decoder(addr_width=30, data_width=32, granularity=8,
                       features={"err", "rty", "stall", "lock", "cti", "bte"})
         sub_1 = Interface(addr_width=14, data_width=32, granularity=8)
-        dut.add(sub_1, addr=0x10000)
+        self.assertEqual(dut.add(sub_1, addr=0x10000),
+                         (0x10000, 0x20000, 1))
         sub_2 = Interface(addr_width=14, data_width=32, granularity=8,
                           features={"err", "rty", "stall", "lock", "cti", "bte"})
-        dut.add(sub_2)
+        self.assertEqual(dut.add(sub_2),
+                         (0x20000, 0x30000, 1))
 
         def sim_test():
             yield dut.bus.adr.eq(0x10400 >> 2)
@@ -167,6 +169,9 @@ class DecoderSimulationTestCase(unittest.TestCase):
             self.assertEqual((yield dut.bus.dat_r), 0xabcdef01)
 
             yield dut.bus.adr.eq(0x20400 >> 2)
+            yield dut.bus.sel.eq(0b1001)
+            yield dut.bus.we.eq(1)
+            yield sub_1.dat_r.eq(0)
             yield sub_1.ack.eq(0)
             yield sub_2.err.eq(1)
             yield sub_2.rty.eq(1)
@@ -176,8 +181,11 @@ class DecoderSimulationTestCase(unittest.TestCase):
             self.assertEqual((yield sub_1.cyc), 0)
             self.assertEqual((yield sub_2.cyc), 1)
             self.assertEqual((yield sub_1.stb), 1)
-            self.assertEqual((yield sub_1.sel), 0b11)
+            self.assertEqual((yield sub_1.sel), 0b1001)
             self.assertEqual((yield sub_1.dat_w), 0x12345678)
+            self.assertEqual((yield sub_2.stb), 1)
+            self.assertEqual((yield sub_2.sel), 0b1001)
+            self.assertEqual((yield sub_2.dat_w), 0x12345678)
             self.assertEqual((yield sub_2.lock), 1)
             self.assertEqual((yield sub_2.cti), CycleType.INCR_BURST.value)
             self.assertEqual((yield sub_2.bte), BurstTypeExt.WRAP_4.value)
@@ -187,6 +195,25 @@ class DecoderSimulationTestCase(unittest.TestCase):
             self.assertEqual((yield dut.bus.stall), 1)
             self.assertEqual((yield dut.bus.dat_r), 0x5678abcd)
 
+            yield dut.bus.adr.eq(0x10400 >> 2)
+            yield dut.bus.sel.eq(0)
+            yield dut.bus.cyc.eq(0)
+            yield dut.bus.stb.eq(0)
+            yield dut.bus.dat_w.eq(0x87654321)
+            yield dut.bus.we.eq(0)
+            yield Delay(1e-6)
+            self.assertEqual((yield sub_1.adr), 0x400 >> 2)
+            self.assertEqual((yield sub_1.cyc), 0)
+            self.assertEqual((yield sub_2.cyc), 0)
+            self.assertEqual((yield sub_1.stb), 0)
+            self.assertEqual((yield sub_1.sel), 0)
+            self.assertEqual((yield sub_1.dat_w), 0x87654321)
+            self.assertEqual((yield sub_2.stb), 0)
+            self.assertEqual((yield sub_2.sel), 0)
+            self.assertEqual((yield sub_2.dat_w), 0x87654321)
+            self.assertEqual((yield dut.bus.ack), 0)
+            self.assertEqual((yield dut.bus.dat_r), 0)
+
         with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
             sim.add_process(sim_test())
             sim.run()
@@ -220,6 +247,13 @@ class DecoderSimulationTestCase(unittest.TestCase):
         self.assertEqual(dut.add(loop_4.bus, addr=0x40000, sparse=True),
                          (0x40000, 0x40100, 1))
 
+        for sig in ["adr", "dat_r", "sel"]:
+            getattr(dut.bus, sig).name = "dec__" + sig
+            getattr(loop_1.bus, sig).name = "sub1__" + sig
+            getattr(loop_2.bus, sig).name = "sub2__" + sig
+            getattr(loop_3.bus, sig).name = "sub3__" + sig
+            getattr(loop_4.bus, sig).name = "sub4__" + sig
+
         def sim_test():
             yield dut.bus.cyc.eq(1)
 
@@ -340,7 +374,7 @@ class ArbiterSimulationTestCase(unittest.TestCase):
         itor_1 = Interface(addr_width=30, data_width=32, granularity=8)
         dut.add(itor_1)
         itor_2 = Interface(addr_width=30, data_width=32, granularity=16,
-                      features={"err", "rty", "stall", "lock", "cti", "bte"})
+                           features={"err", "rty", "stall", "lock", "cti", "bte"})
         dut.add(itor_2)
 
         def sim_test():
@@ -370,7 +404,7 @@ class ArbiterSimulationTestCase(unittest.TestCase):
             yield itor_2.cyc.eq(1)
             yield itor_2.stb.eq(1)
             yield itor_2.sel.eq(0b10)
-            yield itor_2.we.eq(1)
+            yield itor_2.we.eq(0)
             yield itor_2.dat_w.eq(0x43218765)
             yield itor_2.lock.eq(0)
             yield itor_2.cti.eq(CycleType.INCR_BURST)
@@ -385,7 +419,7 @@ class ArbiterSimulationTestCase(unittest.TestCase):
             self.assertEqual((yield dut.bus.cyc), 1)
             self.assertEqual((yield dut.bus.stb), 1)
             self.assertEqual((yield dut.bus.sel), 0b1100)
-            self.assertEqual((yield dut.bus.we), 1)
+            self.assertEqual((yield dut.bus.we), 0)
             self.assertEqual((yield dut.bus.dat_w), 0x43218765)
             self.assertEqual((yield dut.bus.lock), 0)
             self.assertEqual((yield dut.bus.cti), CycleType.INCR_BURST.value)
@@ -585,13 +619,16 @@ class InterconnectSharedSimulationTestCase(unittest.TestCase):
             ("bte",    2, DIR_FANOUT),
             ("err",    1, DIR_FANIN)
         ])
-        self.ram = SRAM(Memory(width=32, depth=2048, init=[]),
-                        granularity=8, features={"err","cti","bte"})
-        self.sub01 = Interface(addr_width=21,
+        self.sub01 = Interface(addr_width=11,
+                             data_width=32,
+                             granularity=8,
+                             features={"err","cti","bte"},
+                             name="sub01")
+        self.sub02 = Interface(addr_width=21,
                                data_width=32,
                                granularity=8,
                                features={"err","cti","bte"},
-                               name="sub01")
+                               name="sub02")
         self.dut = InterconnectShared(
             addr_width=30, data_width=32, granularity=8,
             features={"err","cti","bte"},
@@ -600,8 +637,8 @@ class InterconnectSharedSimulationTestCase(unittest.TestCase):
                 self.master02
             ],
             targets=[
-                (self.ram.bus, 0),
-                (self.sub01, (2**21) << 2)
+                (self.sub01, 0),
+                (self.sub02, (2**21) << 2)
             ]
         )
 
@@ -616,29 +653,27 @@ class InterconnectSharedSimulationTestCase(unittest.TestCase):
                 yield self.master01.cyc.eq(1)
                 yield self.master02.cyc.eq(1)
                 yield
-                ram_cyc = (yield self.ram.bus.cyc)
                 sub01_cyc = (yield self.sub01.cyc)
-                if ram_cyc == 1:
+                sub02_cyc = (yield self.sub02.cyc)
+                if sub01_cyc == 1:
                     yield self.master01.stb.eq(1)
                     yield
-                    yield self.ram.bus.ack.eq(1)
+                    yield self.sub01.ack.eq(1)
                     yield self.master01.stb.eq(0)
                     yield
-                    yield self.ram.bus.ack.eq(0)
+                    yield self.sub01.ack.eq(0)
                     yield self.master01.cyc.eq(0)
-                elif sub01_cyc == 1:
+                elif sub02_cyc == 1:
                     yield self.master02.stb.eq(1)
                     yield
-                    yield self.sub01.ack.eq(1)
+                    yield self.sub02.ack.eq(1)
                     yield self.master02.stb.eq(0)
                     yield
-                    yield self.sub01.ack.eq(0)
+                    yield self.sub02.ack.eq(0)
                     yield self.master02.cyc.eq(0)
                 yield
 
-        m = Module()
-        m.submodules += self.dut, self.ram
-        with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
+        with Simulator(self.dut, vcd_file=open("test.vcd", "w")) as sim:
             sim.add_clock(1e-6)
             sim.add_sync_process(sim_test())
             sim.run()

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index 84faeeda80f7d98b68e6d1565e380e5be1397e23..de5c15d551c081a224590ee4ba8706ca3d2d7547 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -47,15 +47,8 @@ class SRAM(Elaboratable):
                             .format(memory))
         self.memory = memory
         self.read_only = read_only
-        # Define total address space:
-        # - Base: equals memory.depth
-        # - Has an additional ReadPort: add rdport.depth
-        # - Has an additional WirtePort: add wrport.depth
-        self._memdepth = self.memory.depth * 2
-        if not read_only:
-            self._memdepth += self.memory.depth
         if bus is None:
-            bus = Interface(addr_width=max(0, log2_int(self._memdepth, need_pow2=False)),
+            bus = Interface(addr_width=log2_int(self.memory.depth, need_pow2=False),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,