radv: clear FMASK layers instead of the whole buffer on GFX8

This reduces the size of fill operations needed to clear FMASK
for layered color textures.

GFX9 unsupported for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index b336655a913f61938188bfdd3924ecd089504941..05ad181a87a6bc643ae3ae96daf1c5ea0f97e2ee 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -848,6 +848,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
                surf->u.legacy.fmask.tiling_index = fout.tileIndex;
                surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
                surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
+               surf->u.legacy.fmask.slice_size = fout.sliceSize;
 
                /* Compute tile swizzle for FMASK. */
                if (config->info.fmask_surf_index &&

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 49f68f4fc92738c4594b17fe616dcaa065f5c761..aa93e917270c81fed1870dc28cbd0c3378e2447f 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -86,6 +86,7 @@ struct legacy_surf_fmask {
     uint8_t tiling_index;    /* max 31 */
     uint8_t bankh;           /* max 8 */
     uint16_t pitch_in_pixels;
+    uint64_t slice_size;
 };
 
 struct legacy_surf_layout {

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index db855dfc76c2b66c22207f3db5bdf3987dfed476..ef659a6c48ce5cf259f292c76a1f6d05278674f0 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4905,7 +4905,8 @@ static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
 }
 
 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
-                          struct radv_image *image)
+                          struct radv_image *image,
+                          const VkImageSubresourceRange *range)
 {
        struct radv_cmd_state *state = &cmd_buffer->state;
        static const uint32_t fmask_clear_values[4] = {
@@ -4920,7 +4921,7 @@ void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
 
-       state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
+       state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
 
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
 }
@@ -5008,7 +5009,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
        }
 
        if (radv_image_has_fmask(image)) {
-               radv_initialize_fmask(cmd_buffer, image);
+               radv_initialize_fmask(cmd_buffer, image, range);
        }
 
        if (radv_dcc_enabled(image, range->baseMipLevel)) {

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index cf3f0eb1d55954b113fa81df24cb20618971428c..ca007d1dd65e8e7014c0fecded201ecf3d160e21 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -907,6 +907,7 @@ radv_image_get_fmask_info(struct radv_device *device,
        out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
        out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
        out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
+       out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
        out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
        out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
        out->alignment = image->planes[0].surface.fmask_alignment;

diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 5880064ff30ed307db72ec0d1725b98fb42f6d75..30981f00790ea214fd974dc5e5417d3485b7bf63 100644 (file)
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -214,7 +214,8 @@ void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
 uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
                          struct radv_image *image, uint32_t value);
 uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
-                         struct radv_image *image, uint32_t value);
+                         struct radv_image *image,
+                         const VkImageSubresourceRange *range, uint32_t value);
 uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
                        struct radv_image *image,
                        const VkImageSubresourceRange *range, uint32_t value);

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index c3def76e957510ca537e4a792ca5a68d8fc021cc..0a9d9e76ca424422ce9a9a647c0b230ab4da1582 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1336,11 +1336,25 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
 
 uint32_t
 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
-                struct radv_image *image, uint32_t value)
+                struct radv_image *image,
+                const VkImageSubresourceRange *range, uint32_t value)
 {
-       return radv_fill_buffer(cmd_buffer, image->bo,
-                               image->offset + image->fmask.offset,
-                               image->fmask.size, value);
+       uint64_t offset = image->offset + image->fmask.offset;
+       uint64_t size;
+
+       /* MSAA images do not support mipmap levels. */
+       assert(range->baseMipLevel == 0 &&
+              radv_get_levelCount(image, range) == 1);
+
+       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+               /* TODO: clear layers. */
+               size = image->fmask.size;
+       } else {
+               offset += image->fmask.slice_size * range->baseArrayLayer;
+               size = image->fmask.slice_size * radv_get_layerCount(image, range);
+       }
+
+       return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
 }
 
 uint32_t

diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c
index e5d0868aab5b747944c6ebbf097c9ed59f04a34b..a8f5e0cc4c191245a943fba5bd89ffa9ba81d075 100644 (file)
--- a/src/amd/vulkan/radv_meta_fmask_expand.c
+++ b/src/amd/vulkan/radv_meta_fmask_expand.c
@@ -172,7 +172,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
                                        RADV_CMD_FLAG_INV_GLOBAL_L2;
 
        /* Re-initialize FMASK in fully expanded mode. */
-       radv_initialize_fmask(cmd_buffer, image);
+       radv_initialize_fmask(cmd_buffer, image, subresourceRange);
 }
 
 void radv_device_finish_meta_fmask_expand_state(struct radv_device *device)

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1249ad0445dbddf0029a5818b055b2e1157f0718..fd7baa5f5b573906130b0f0a89a8fc8bb36d9289 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1555,6 +1555,7 @@ struct radv_fmask_info {
        unsigned slice_tile_max;
        unsigned tile_mode_index;
        unsigned tile_swizzle;
+       uint64_t slice_size;
 };
 
 struct radv_cmask_info {
@@ -2081,7 +2082,8 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
                         const VkImageSubresourceRange *range, uint32_t value);
 
 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
-                          struct radv_image *image);
+                          struct radv_image *image,
+                          const VkImageSubresourceRange *range);
 
 struct radv_fence {
        struct radeon_winsys_fence *fence;