projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: clear FMASK layers instead of the whole buffer on GFX8
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
933 }
934
935 if (mask & RADV_PREFETCH_PS)
936 radv_emit_shader_prefetch(cmd_buffer,
937 pipeline->shaders[MESA_SHADER_FRAGMENT]);
938
939 state->prefetch_L2_mask &= ~mask;
940 }
941
942 static void
943 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->device->physical_device->rbplus_allowed)
946 return;
947
948 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
949 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
950 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
951
952 unsigned sx_ps_downconvert = 0;
953 unsigned sx_blend_opt_epsilon = 0;
954 unsigned sx_blend_opt_control = 0;
955
956 for (unsigned i = 0; i < subpass->color_count; ++i) {
957 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
958 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
959 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
960 continue;
961 }
962
963 int idx = subpass->color_attachments[i].attachment;
964 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
965
966 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
967 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
968 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
969 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
970
971 bool has_alpha, has_rgb;
972
973 /* Set if RGB and A are present. */
974 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
975
976 if (format == V_028C70_COLOR_8 ||
977 format == V_028C70_COLOR_16 ||
978 format == V_028C70_COLOR_32)
979 has_rgb = !has_alpha;
980 else
981 has_rgb = true;
982
983 /* Check the colormask and export format. */
984 if (!(colormask & 0x7))
985 has_rgb = false;
986 if (!(colormask & 0x8))
987 has_alpha = false;
988
989 if (spi_format == V_028714_SPI_SHADER_ZERO) {
990 has_rgb = false;
991 has_alpha = false;
992 }
993
994 /* Disable value checking for disabled channels. */
995 if (!has_rgb)
996 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
997 if (!has_alpha)
998 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
999
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1001 switch (format) {
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1010 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1011 }
1012 break;
1013
1014 case V_028C70_COLOR_5_6_5:
1015 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1016 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1017 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1018 }
1019 break;
1020
1021 case V_028C70_COLOR_1_5_5_5:
1022 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1023 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1024 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1025 }
1026 break;
1027
1028 case V_028C70_COLOR_4_4_4_4:
1029 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1031 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1032 }
1033 break;
1034
1035 case V_028C70_COLOR_32:
1036 if (swap == V_028C70_SWAP_STD &&
1037 spi_format == V_028714_SPI_SHADER_32_R)
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 else if (swap == V_028C70_SWAP_ALT_REV &&
1040 spi_format == V_028714_SPI_SHADER_32_AR)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1042 break;
1043
1044 case V_028C70_COLOR_16:
1045 case V_028C70_COLOR_16_16:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 if (swap == V_028C70_SWAP_STD ||
1052 swap == V_028C70_SWAP_STD_REV)
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1054 else
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_2_10_10_10:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072 }
1073 }
1074
1075 for (unsigned i = subpass->color_count; i < 8; ++i) {
1076 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078 }
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1081 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1084
1085 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1086 }
1087
1088 static void
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1092
1093 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1094 return;
1095
1096 radv_update_multisample_state(cmd_buffer, pipeline);
1097
1098 cmd_buffer->scratch_size_needed =
1099 MAX2(cmd_buffer->scratch_size_needed,
1100 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1101
1102 if (!cmd_buffer->state.emitted_pipeline ||
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1104 pipeline->graphics.can_use_guardband)
1105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1106
1107 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1108
1109 if (!cmd_buffer->state.emitted_pipeline ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1112 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1113 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1114 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1115 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1116 }
1117
1118 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1119 if (!pipeline->shaders[i])
1120 continue;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1123 pipeline->shaders[i]->bo);
1124 }
1125
1126 if (radv_pipeline_has_gs(pipeline))
1127 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1128 pipeline->gs_copy_shader->bo);
1129
1130 if (unlikely(cmd_buffer->device->trace_bo))
1131 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1132
1133 cmd_buffer->state.emitted_pipeline = pipeline;
1134
1135 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1136 }
1137
1138 static void
1139 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1142 cmd_buffer->state.dynamic.viewport.viewports);
1143 }
1144
1145 static void
1146 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1149
1150 si_write_scissors(cmd_buffer->cs, 0, count,
1151 cmd_buffer->state.dynamic.scissor.scissors,
1152 cmd_buffer->state.dynamic.viewport.viewports,
1153 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1154
1155 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1156 }
1157
1158 static void
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1162 return;
1163
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1165 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1166 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1167 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1168 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1169 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1170 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1171 }
1172 }
1173
1174 static void
1175 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1176 {
1177 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1178
1179 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1180 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1181 }
1182
1183 static void
1184 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1187
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1189 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1190 }
1191
1192 static void
1193 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs,
1198 R_028430_DB_STENCILREFMASK, 2);
1199 radeon_emit(cmd_buffer->cs,
1200 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1201 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1202 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer->cs,
1205 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1206 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1207 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1208 S_028434_STENCILOPVAL_BF(1));
1209 }
1210
1211 static void
1212 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1215
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1217 fui(d->depth_bounds.min));
1218 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1219 fui(d->depth_bounds.max));
1220 }
1221
1222 static void
1223 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1232 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1233 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1237 }
1238
1239 static void
1240 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1241 int index,
1242 struct radv_attachment_info *att,
1243 struct radv_image_view *iview,
1244 VkImageLayout layout)
1245 {
1246 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1247 struct radv_color_buffer_info *cb = &att->cb;
1248 uint32_t cb_color_info = cb->cb_color_info;
1249 struct radv_image *image = iview->image;
1250
1251 if (!radv_layout_dcc_compressed(image, layout,
1252 radv_image_queue_family_mask(image,
1253 cmd_buffer->queue_family_index,
1254 cmd_buffer->queue_family_index))) {
1255 cb_color_info &= C_028C70_DCC_ENABLE;
1256 }
1257
1258 if (radv_image_is_tc_compat_cmask(image) &&
1259 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1260 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1261 /* If this bit is set, the FMASK decompression operation
1262 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1263 */
1264 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1265 }
1266
1267 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1268 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1269 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1270 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1271 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1272 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1273 radeon_emit(cmd_buffer->cs, cb_color_info);
1274 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1275 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1276 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1277 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1278 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1279 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1280
1281 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1282 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1283 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1284
1285 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1286 cb->cb_mrt_epitch);
1287 } else {
1288 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1289 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1290 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1291 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1292 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1293 radeon_emit(cmd_buffer->cs, cb_color_info);
1294 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1295 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1296 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1297 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1298 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1299 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1300
1301 if (is_vi) { /* DCC BASE */
1302 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1303 }
1304 }
1305
1306 if (radv_dcc_enabled(image, iview->base_mip)) {
1307 /* Drawing with DCC enabled also compresses colorbuffers. */
1308 VkImageSubresourceRange range = {
1309 .aspectMask = iview->aspect_mask,
1310 .baseMipLevel = iview->base_mip,
1311 .levelCount = iview->level_count,
1312 .baseArrayLayer = iview->base_layer,
1313 .layerCount = iview->layer_count,
1314 };
1315
1316 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1317 }
1318 }
1319
1320 static void
1321 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1322 struct radv_ds_buffer_info *ds,
1323 struct radv_image *image, VkImageLayout layout,
1324 bool requires_cond_exec)
1325 {
1326 uint32_t db_z_info = ds->db_z_info;
1327 uint32_t db_z_info_reg;
1328
1329 if (!radv_image_is_tc_compat_htile(image))
1330 return;
1331
1332 if (!radv_layout_has_htile(image, layout,
1333 radv_image_queue_family_mask(image,
1334 cmd_buffer->queue_family_index,
1335 cmd_buffer->queue_family_index))) {
1336 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1337 }
1338
1339 db_z_info &= C_028040_ZRANGE_PRECISION;
1340
1341 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1342 db_z_info_reg = R_028038_DB_Z_INFO;
1343 } else {
1344 db_z_info_reg = R_028040_DB_Z_INFO;
1345 }
1346
1347 /* When we don't know the last fast clear value we need to emit a
1348 * conditional packet that will eventually skip the following
1349 * SET_CONTEXT_REG packet.
1350 */
1351 if (requires_cond_exec) {
1352 uint64_t va = radv_buffer_get_va(image->bo);
1353 va += image->offset + image->tc_compat_zrange_offset;
1354
1355 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1356 radeon_emit(cmd_buffer->cs, va);
1357 radeon_emit(cmd_buffer->cs, va >> 32);
1358 radeon_emit(cmd_buffer->cs, 0);
1359 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1360 }
1361
1362 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1363 }
1364
1365 static void
1366 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1367 struct radv_ds_buffer_info *ds,
1368 struct radv_image *image,
1369 VkImageLayout layout)
1370 {
1371 uint32_t db_z_info = ds->db_z_info;
1372 uint32_t db_stencil_info = ds->db_stencil_info;
1373
1374 if (!radv_layout_has_htile(image, layout,
1375 radv_image_queue_family_mask(image,
1376 cmd_buffer->queue_family_index,
1377 cmd_buffer->queue_family_index))) {
1378 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1379 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1380 }
1381
1382 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1383 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1384
1385
1386 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1387 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1388 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1389 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1390 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1391
1392 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1393 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1394 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1395 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1396 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1397 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1398 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1399 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1400 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1401 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1402 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1403
1404 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1405 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1406 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1407 } else {
1408 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1409
1410 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1411 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1412 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1413 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1414 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1415 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1416 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1417 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1418 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1419 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1420
1421 }
1422
1423 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1424 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1425
1426 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1427 ds->pa_su_poly_offset_db_fmt_cntl);
1428 }
1429
1430 /**
1431 * Update the fast clear depth/stencil values if the image is bound as a
1432 * depth/stencil buffer.
1433 */
1434 static void
1435 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1436 struct radv_image *image,
1437 VkClearDepthStencilValue ds_clear_value,
1438 VkImageAspectFlags aspects)
1439 {
1440 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1441 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1442 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1443 struct radv_attachment_info *att;
1444 uint32_t att_idx;
1445
1446 if (!framebuffer || !subpass)
1447 return;
1448
1449 if (!subpass->depth_stencil_attachment)
1450 return;
1451
1452 att_idx = subpass->depth_stencil_attachment->attachment;
1453 att = &framebuffer->attachments[att_idx];
1454 if (att->attachment->image != image)
1455 return;
1456
1457 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1458 radeon_emit(cs, ds_clear_value.stencil);
1459 radeon_emit(cs, fui(ds_clear_value.depth));
1460
1461 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1462 * only needed when clearing Z to 0.0.
1463 */
1464 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1465 ds_clear_value.depth == 0.0) {
1466 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1467
1468 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1469 layout, false);
1470 }
1471
1472 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1473 }
1474
1475 /**
1476 * Set the clear depth/stencil values to the image's metadata.
1477 */
1478 static void
1479 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1480 struct radv_image *image,
1481 VkClearDepthStencilValue ds_clear_value,
1482 VkImageAspectFlags aspects)
1483 {
1484 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1485 uint64_t va = radv_buffer_get_va(image->bo);
1486 unsigned reg_offset = 0, reg_count = 0;
1487
1488 va += image->offset + image->clear_value_offset;
1489
1490 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1491 ++reg_count;
1492 } else {
1493 ++reg_offset;
1494 va += 4;
1495 }
1496 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1497 ++reg_count;
1498
1499 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1500 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1501 S_370_WR_CONFIRM(1) |
1502 S_370_ENGINE_SEL(V_370_PFP));
1503 radeon_emit(cs, va);
1504 radeon_emit(cs, va >> 32);
1505 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1506 radeon_emit(cs, ds_clear_value.stencil);
1507 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1508 radeon_emit(cs, fui(ds_clear_value.depth));
1509 }
1510
1511 /**
1512 * Update the TC-compat metadata value for this image.
1513 */
1514 static void
1515 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1516 struct radv_image *image,
1517 uint32_t value)
1518 {
1519 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1520 uint64_t va = radv_buffer_get_va(image->bo);
1521 va += image->offset + image->tc_compat_zrange_offset;
1522
1523 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1524 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1525 S_370_WR_CONFIRM(1) |
1526 S_370_ENGINE_SEL(V_370_PFP));
1527 radeon_emit(cs, va);
1528 radeon_emit(cs, va >> 32);
1529 radeon_emit(cs, value);
1530 }
1531
1532 static void
1533 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1534 struct radv_image *image,
1535 VkClearDepthStencilValue ds_clear_value)
1536 {
1537 uint64_t va = radv_buffer_get_va(image->bo);
1538 va += image->offset + image->tc_compat_zrange_offset;
1539 uint32_t cond_val;
1540
1541 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1542 * depth clear value is 0.0f.
1543 */
1544 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1545
1546 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1547 }
1548
1549 /**
1550 * Update the clear depth/stencil values for this image.
1551 */
1552 void
1553 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1554 struct radv_image *image,
1555 VkClearDepthStencilValue ds_clear_value,
1556 VkImageAspectFlags aspects)
1557 {
1558 assert(radv_image_has_htile(image));
1559
1560 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1561
1562 if (radv_image_is_tc_compat_htile(image) &&
1563 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1564 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1565 ds_clear_value);
1566 }
1567
1568 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1569 aspects);
1570 }
1571
1572 /**
1573 * Load the clear depth/stencil values from the image's metadata.
1574 */
1575 static void
1576 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1577 struct radv_image *image)
1578 {
1579 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1580 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1581 uint64_t va = radv_buffer_get_va(image->bo);
1582 unsigned reg_offset = 0, reg_count = 0;
1583
1584 va += image->offset + image->clear_value_offset;
1585
1586 if (!radv_image_has_htile(image))
1587 return;
1588
1589 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1590 ++reg_count;
1591 } else {
1592 ++reg_offset;
1593 va += 4;
1594 }
1595 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1596 ++reg_count;
1597
1598 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1599
1600 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1601 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1602 radeon_emit(cs, va);
1603 radeon_emit(cs, va >> 32);
1604 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1605 radeon_emit(cs, reg_count);
1606 } else {
1607 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1608 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1609 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1610 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1611 radeon_emit(cs, va);
1612 radeon_emit(cs, va >> 32);
1613 radeon_emit(cs, reg >> 2);
1614 radeon_emit(cs, 0);
1615
1616 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1617 radeon_emit(cs, 0);
1618 }
1619 }
1620
1621 /*
1622 * With DCC some colors don't require CMASK elimination before being
1623 * used as a texture. This sets a predicate value to determine if the
1624 * cmask eliminate is required.
1625 */
1626 void
1627 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1628 struct radv_image *image,
1629 const VkImageSubresourceRange *range, bool value)
1630 {
1631 uint64_t pred_val = value;
1632 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1633 uint32_t level_count = radv_get_levelCount(image, range);
1634 uint32_t count = 2 * level_count;
1635
1636 assert(radv_dcc_enabled(image, range->baseMipLevel));
1637
1638 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1639 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1640 S_370_WR_CONFIRM(1) |
1641 S_370_ENGINE_SEL(V_370_PFP));
1642 radeon_emit(cmd_buffer->cs, va);
1643 radeon_emit(cmd_buffer->cs, va >> 32);
1644
1645 for (uint32_t l = 0; l < level_count; l++) {
1646 radeon_emit(cmd_buffer->cs, pred_val);
1647 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1648 }
1649 }
1650
1651 /**
1652 * Update the DCC predicate to reflect the compression state.
1653 */
1654 void
1655 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1656 struct radv_image *image,
1657 const VkImageSubresourceRange *range, bool value)
1658 {
1659 uint64_t pred_val = value;
1660 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1661 uint32_t level_count = radv_get_levelCount(image, range);
1662 uint32_t count = 2 * level_count;
1663
1664 assert(radv_dcc_enabled(image, range->baseMipLevel));
1665
1666 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1667 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1668 S_370_WR_CONFIRM(1) |
1669 S_370_ENGINE_SEL(V_370_PFP));
1670 radeon_emit(cmd_buffer->cs, va);
1671 radeon_emit(cmd_buffer->cs, va >> 32);
1672
1673 for (uint32_t l = 0; l < level_count; l++) {
1674 radeon_emit(cmd_buffer->cs, pred_val);
1675 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1676 }
1677 }
1678
1679 /**
1680 * Update the fast clear color values if the image is bound as a color buffer.
1681 */
1682 static void
1683 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1684 struct radv_image *image,
1685 int cb_idx,
1686 uint32_t color_values[2])
1687 {
1688 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1689 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1690 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1691 struct radv_attachment_info *att;
1692 uint32_t att_idx;
1693
1694 if (!framebuffer || !subpass)
1695 return;
1696
1697 att_idx = subpass->color_attachments[cb_idx].attachment;
1698 if (att_idx == VK_ATTACHMENT_UNUSED)
1699 return;
1700
1701 att = &framebuffer->attachments[att_idx];
1702 if (att->attachment->image != image)
1703 return;
1704
1705 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1706 radeon_emit(cs, color_values[0]);
1707 radeon_emit(cs, color_values[1]);
1708
1709 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1710 }
1711
1712 /**
1713 * Set the clear color values to the image's metadata.
1714 */
1715 static void
1716 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1717 struct radv_image *image,
1718 const VkImageSubresourceRange *range,
1719 uint32_t color_values[2])
1720 {
1721 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1722 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1723 uint32_t level_count = radv_get_levelCount(image, range);
1724 uint32_t count = 2 * level_count;
1725
1726 assert(radv_image_has_cmask(image) ||
1727 radv_dcc_enabled(image, range->baseMipLevel));
1728
1729 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1730 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1731 S_370_WR_CONFIRM(1) |
1732 S_370_ENGINE_SEL(V_370_PFP));
1733 radeon_emit(cs, va);
1734 radeon_emit(cs, va >> 32);
1735
1736 for (uint32_t l = 0; l < level_count; l++) {
1737 radeon_emit(cs, color_values[0]);
1738 radeon_emit(cs, color_values[1]);
1739 }
1740 }
1741
1742 /**
1743 * Update the clear color values for this image.
1744 */
1745 void
1746 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1747 const struct radv_image_view *iview,
1748 int cb_idx,
1749 uint32_t color_values[2])
1750 {
1751 struct radv_image *image = iview->image;
1752 VkImageSubresourceRange range = {
1753 .aspectMask = iview->aspect_mask,
1754 .baseMipLevel = iview->base_mip,
1755 .levelCount = iview->level_count,
1756 .baseArrayLayer = iview->base_layer,
1757 .layerCount = iview->layer_count,
1758 };
1759
1760 assert(radv_image_has_cmask(image) ||
1761 radv_dcc_enabled(image, iview->base_mip));
1762
1763 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1764
1765 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1766 color_values);
1767 }
1768
1769 /**
1770 * Load the clear color values from the image's metadata.
1771 */
1772 static void
1773 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1774 struct radv_image_view *iview,
1775 int cb_idx)
1776 {
1777 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1778 struct radv_image *image = iview->image;
1779 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1780
1781 if (!radv_image_has_cmask(image) &&
1782 !radv_dcc_enabled(image, iview->base_mip))
1783 return;
1784
1785 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1786
1787 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1788 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1789 radeon_emit(cs, va);
1790 radeon_emit(cs, va >> 32);
1791 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1792 radeon_emit(cs, 2);
1793 } else {
1794 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1795 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1796 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1797 COPY_DATA_COUNT_SEL);
1798 radeon_emit(cs, va);
1799 radeon_emit(cs, va >> 32);
1800 radeon_emit(cs, reg >> 2);
1801 radeon_emit(cs, 0);
1802
1803 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1804 radeon_emit(cs, 0);
1805 }
1806 }
1807
1808 static void
1809 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1810 {
1811 int i;
1812 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1813 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1814 unsigned num_bpp64_colorbufs = 0;
1815
1816 /* this may happen for inherited secondary recording */
1817 if (!framebuffer)
1818 return;
1819
1820 for (i = 0; i < 8; ++i) {
1821 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1822 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1823 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1824 continue;
1825 }
1826
1827 int idx = subpass->color_attachments[i].attachment;
1828 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1829 struct radv_image_view *iview = att->attachment;
1830 struct radv_image *image = iview->image;
1831 VkImageLayout layout = subpass->color_attachments[i].layout;
1832
1833 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1834
1835 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1836 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1837 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1838
1839 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1840
1841 if (image->planes[0].surface.bpe >= 8)
1842 num_bpp64_colorbufs++;
1843 }
1844
1845 if (subpass->depth_stencil_attachment) {
1846 int idx = subpass->depth_stencil_attachment->attachment;
1847 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1848 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1849 struct radv_image *image = att->attachment->image;
1850 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1851 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1852 cmd_buffer->queue_family_index,
1853 cmd_buffer->queue_family_index);
1854 /* We currently don't support writing decompressed HTILE */
1855 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1856 radv_layout_is_htile_compressed(image, layout, queue_mask));
1857
1858 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1859
1860 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1861 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1862 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1863 }
1864 radv_load_ds_clear_metadata(cmd_buffer, image);
1865 } else {
1866 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1867 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1868 else
1869 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1870
1871 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1872 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1873 }
1874 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1875 S_028208_BR_X(framebuffer->width) |
1876 S_028208_BR_Y(framebuffer->height));
1877
1878 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1879 uint8_t watermark = 4; /* Default value for GFX8. */
1880
1881 /* For optimal DCC performance. */
1882 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1883 if (num_bpp64_colorbufs >= 5) {
1884 watermark = 8;
1885 } else {
1886 watermark = 6;
1887 }
1888 }
1889
1890 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1891 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1892 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1893 }
1894
1895 if (cmd_buffer->device->dfsm_allowed) {
1896 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1897 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1898 }
1899
1900 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1901 }
1902
1903 static void
1904 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1905 {
1906 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1907 struct radv_cmd_state *state = &cmd_buffer->state;
1908
1909 if (state->index_type != state->last_index_type) {
1910 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1911 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1912 2, state->index_type);
1913 } else {
1914 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1915 radeon_emit(cs, state->index_type);
1916 }
1917
1918 state->last_index_type = state->index_type;
1919 }
1920
1921 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1922 radeon_emit(cs, state->index_va);
1923 radeon_emit(cs, state->index_va >> 32);
1924
1925 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1926 radeon_emit(cs, state->max_index_count);
1927
1928 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1929 }
1930
1931 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1932 {
1933 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1934 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1935 uint32_t pa_sc_mode_cntl_1 =
1936 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1937 uint32_t db_count_control;
1938
1939 if(!cmd_buffer->state.active_occlusion_queries) {
1940 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1941 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1942 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1943 has_perfect_queries) {
1944 /* Re-enable out-of-order rasterization if the
1945 * bound pipeline supports it and if it's has
1946 * been disabled before starting any perfect
1947 * occlusion queries.
1948 */
1949 radeon_set_context_reg(cmd_buffer->cs,
1950 R_028A4C_PA_SC_MODE_CNTL_1,
1951 pa_sc_mode_cntl_1);
1952 }
1953 }
1954 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1955 } else {
1956 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1957 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1958
1959 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1960 db_count_control =
1961 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1962 S_028004_SAMPLE_RATE(sample_rate) |
1963 S_028004_ZPASS_ENABLE(1) |
1964 S_028004_SLICE_EVEN_ENABLE(1) |
1965 S_028004_SLICE_ODD_ENABLE(1);
1966
1967 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1968 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1969 has_perfect_queries) {
1970 /* If the bound pipeline has enabled
1971 * out-of-order rasterization, we should
1972 * disable it before starting any perfect
1973 * occlusion queries.
1974 */
1975 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1976
1977 radeon_set_context_reg(cmd_buffer->cs,
1978 R_028A4C_PA_SC_MODE_CNTL_1,
1979 pa_sc_mode_cntl_1);
1980 }
1981 } else {
1982 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1983 S_028004_SAMPLE_RATE(sample_rate);
1984 }
1985 }
1986
1987 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1988
1989 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1990 }
1991
1992 static void
1993 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1994 {
1995 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1996
1997 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1998 radv_emit_viewport(cmd_buffer);
1999
2000 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2001 !cmd_buffer->device->physical_device->has_scissor_bug)
2002 radv_emit_scissor(cmd_buffer);
2003
2004 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2005 radv_emit_line_width(cmd_buffer);
2006
2007 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2008 radv_emit_blend_constants(cmd_buffer);
2009
2010 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2011 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2012 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2013 radv_emit_stencil(cmd_buffer);
2014
2015 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2016 radv_emit_depth_bounds(cmd_buffer);
2017
2018 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2019 radv_emit_depth_bias(cmd_buffer);
2020
2021 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2022 radv_emit_discard_rectangle(cmd_buffer);
2023
2024 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2025 radv_emit_sample_locations(cmd_buffer);
2026
2027 cmd_buffer->state.dirty &= ~states;
2028 }
2029
2030 static void
2031 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2032 VkPipelineBindPoint bind_point)
2033 {
2034 struct radv_descriptor_state *descriptors_state =
2035 radv_get_descriptors_state(cmd_buffer, bind_point);
2036 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2037 unsigned bo_offset;
2038
2039 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2040 set->mapped_ptr,
2041 &bo_offset))
2042 return;
2043
2044 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2045 set->va += bo_offset;
2046 }
2047
2048 static void
2049 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2050 VkPipelineBindPoint bind_point)
2051 {
2052 struct radv_descriptor_state *descriptors_state =
2053 radv_get_descriptors_state(cmd_buffer, bind_point);
2054 uint32_t size = MAX_SETS * 4;
2055 uint32_t offset;
2056 void *ptr;
2057
2058 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2059 256, &offset, &ptr))
2060 return;
2061
2062 for (unsigned i = 0; i < MAX_SETS; i++) {
2063 uint32_t *uptr = ((uint32_t *)ptr) + i;
2064 uint64_t set_va = 0;
2065 struct radv_descriptor_set *set = descriptors_state->sets[i];
2066 if (descriptors_state->valid & (1u << i))
2067 set_va = set->va;
2068 uptr[0] = set_va & 0xffffffff;
2069 }
2070
2071 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2072 va += offset;
2073
2074 if (cmd_buffer->state.pipeline) {
2075 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2076 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2077 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2078
2079 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2080 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2081 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2082
2083 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2084 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2085 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2086
2087 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2088 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2089 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2090
2091 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2092 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2093 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2094 }
2095
2096 if (cmd_buffer->state.compute_pipeline)
2097 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2098 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2099 }
2100
2101 static void
2102 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2103 VkShaderStageFlags stages)
2104 {
2105 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2106 VK_PIPELINE_BIND_POINT_COMPUTE :
2107 VK_PIPELINE_BIND_POINT_GRAPHICS;
2108 struct radv_descriptor_state *descriptors_state =
2109 radv_get_descriptors_state(cmd_buffer, bind_point);
2110 struct radv_cmd_state *state = &cmd_buffer->state;
2111 bool flush_indirect_descriptors;
2112
2113 if (!descriptors_state->dirty)
2114 return;
2115
2116 if (descriptors_state->push_dirty)
2117 radv_flush_push_descriptors(cmd_buffer, bind_point);
2118
2119 flush_indirect_descriptors =
2120 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2121 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2122 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2123 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2124
2125 if (flush_indirect_descriptors)
2126 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2127
2128 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2129 cmd_buffer->cs,
2130 MAX_SETS * MESA_SHADER_STAGES * 4);
2131
2132 if (cmd_buffer->state.pipeline) {
2133 radv_foreach_stage(stage, stages) {
2134 if (!cmd_buffer->state.pipeline->shaders[stage])
2135 continue;
2136
2137 radv_emit_descriptor_pointers(cmd_buffer,
2138 cmd_buffer->state.pipeline,
2139 descriptors_state, stage);
2140 }
2141 }
2142
2143 if (cmd_buffer->state.compute_pipeline &&
2144 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2145 radv_emit_descriptor_pointers(cmd_buffer,
2146 cmd_buffer->state.compute_pipeline,
2147 descriptors_state,
2148 MESA_SHADER_COMPUTE);
2149 }
2150
2151 descriptors_state->dirty = 0;
2152 descriptors_state->push_dirty = false;
2153
2154 assert(cmd_buffer->cs->cdw <= cdw_max);
2155
2156 if (unlikely(cmd_buffer->device->trace_bo))
2157 radv_save_descriptors(cmd_buffer, bind_point);
2158 }
2159
2160 static void
2161 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2162 VkShaderStageFlags stages)
2163 {
2164 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2165 ? cmd_buffer->state.compute_pipeline
2166 : cmd_buffer->state.pipeline;
2167 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2168 VK_PIPELINE_BIND_POINT_COMPUTE :
2169 VK_PIPELINE_BIND_POINT_GRAPHICS;
2170 struct radv_descriptor_state *descriptors_state =
2171 radv_get_descriptors_state(cmd_buffer, bind_point);
2172 struct radv_pipeline_layout *layout = pipeline->layout;
2173 struct radv_shader_variant *shader, *prev_shader;
2174 bool need_push_constants = false;
2175 unsigned offset;
2176 void *ptr;
2177 uint64_t va;
2178
2179 stages &= cmd_buffer->push_constant_stages;
2180 if (!stages ||
2181 (!layout->push_constant_size && !layout->dynamic_offset_count))
2182 return;
2183
2184 radv_foreach_stage(stage, stages) {
2185 if (!pipeline->shaders[stage])
2186 continue;
2187
2188 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2189 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2190
2191 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2192 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2193
2194 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2195 AC_UD_INLINE_PUSH_CONSTANTS,
2196 count,
2197 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2198 }
2199
2200 if (need_push_constants) {
2201 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2202 16 * layout->dynamic_offset_count,
2203 256, &offset, &ptr))
2204 return;
2205
2206 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2207 memcpy((char*)ptr + layout->push_constant_size,
2208 descriptors_state->dynamic_buffers,
2209 16 * layout->dynamic_offset_count);
2210
2211 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2212 va += offset;
2213
2214 MAYBE_UNUSED unsigned cdw_max =
2215 radeon_check_space(cmd_buffer->device->ws,
2216 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2217
2218 prev_shader = NULL;
2219 radv_foreach_stage(stage, stages) {
2220 shader = radv_get_shader(pipeline, stage);
2221
2222 /* Avoid redundantly emitting the address for merged stages. */
2223 if (shader && shader != prev_shader) {
2224 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2225 AC_UD_PUSH_CONSTANTS, va);
2226
2227 prev_shader = shader;
2228 }
2229 }
2230 assert(cmd_buffer->cs->cdw <= cdw_max);
2231 }
2232
2233 cmd_buffer->push_constant_stages &= ~stages;
2234 }
2235
2236 static void
2237 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2238 bool pipeline_is_dirty)
2239 {
2240 if ((pipeline_is_dirty ||
2241 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2242 cmd_buffer->state.pipeline->num_vertex_bindings &&
2243 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2244 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2245 unsigned vb_offset;
2246 void *vb_ptr;
2247 uint32_t i = 0;
2248 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2249 uint64_t va;
2250
2251 /* allocate some descriptor state for vertex buffers */
2252 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2253 &vb_offset, &vb_ptr))
2254 return;
2255
2256 for (i = 0; i < count; i++) {
2257 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2258 uint32_t offset;
2259 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2260 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2261
2262 if (!buffer)
2263 continue;
2264
2265 va = radv_buffer_get_va(buffer->bo);
2266
2267 offset = cmd_buffer->vertex_bindings[i].offset;
2268 va += offset + buffer->offset;
2269 desc[0] = va;
2270 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2271 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2272 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2273 else
2274 desc[2] = buffer->size - offset;
2275 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2276 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2277 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2278 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2279 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2281 }
2282
2283 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2284 va += vb_offset;
2285
2286 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2287 AC_UD_VS_VERTEX_BUFFERS, va);
2288
2289 cmd_buffer->state.vb_va = va;
2290 cmd_buffer->state.vb_size = count * 16;
2291 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2292 }
2293 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2294 }
2295
2296 static void
2297 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2298 {
2299 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2300 struct radv_userdata_info *loc;
2301 uint32_t base_reg;
2302
2303 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2304 if (!radv_get_shader(pipeline, stage))
2305 continue;
2306
2307 loc = radv_lookup_user_sgpr(pipeline, stage,
2308 AC_UD_STREAMOUT_BUFFERS);
2309 if (loc->sgpr_idx == -1)
2310 continue;
2311
2312 base_reg = pipeline->user_data_0[stage];
2313
2314 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2315 base_reg + loc->sgpr_idx * 4, va, false);
2316 }
2317
2318 if (pipeline->gs_copy_shader) {
2319 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2320 if (loc->sgpr_idx != -1) {
2321 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2322
2323 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2324 base_reg + loc->sgpr_idx * 4, va, false);
2325 }
2326 }
2327 }
2328
2329 static void
2330 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2331 {
2332 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2333 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2334 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2335 unsigned so_offset;
2336 void *so_ptr;
2337 uint64_t va;
2338
2339 /* Allocate some descriptor state for streamout buffers. */
2340 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2341 MAX_SO_BUFFERS * 16, 256,
2342 &so_offset, &so_ptr))
2343 return;
2344
2345 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2346 struct radv_buffer *buffer = sb[i].buffer;
2347 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2348
2349 if (!(so->enabled_mask & (1 << i)))
2350 continue;
2351
2352 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2353
2354 va += sb[i].offset;
2355
2356 /* Set the descriptor.
2357 *
2358 * On GFX8, the format must be non-INVALID, otherwise
2359 * the buffer will be considered not bound and store
2360 * instructions will be no-ops.
2361 */
2362 desc[0] = va;
2363 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2364 desc[2] = 0xffffffff;
2365 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2366 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2367 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2368 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2369 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2370 }
2371
2372 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2373 va += so_offset;
2374
2375 radv_emit_streamout_buffers(cmd_buffer, va);
2376 }
2377
2378 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2379 }
2380
2381 static void
2382 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2383 {
2384 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2385 radv_flush_streamout_descriptors(cmd_buffer);
2386 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2387 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2388 }
2389
2390 struct radv_draw_info {
2391 /**
2392 * Number of vertices.
2393 */
2394 uint32_t count;
2395
2396 /**
2397 * Index of the first vertex.
2398 */
2399 int32_t vertex_offset;
2400
2401 /**
2402 * First instance id.
2403 */
2404 uint32_t first_instance;
2405
2406 /**
2407 * Number of instances.
2408 */
2409 uint32_t instance_count;
2410
2411 /**
2412 * First index (indexed draws only).
2413 */
2414 uint32_t first_index;
2415
2416 /**
2417 * Whether it's an indexed draw.
2418 */
2419 bool indexed;
2420
2421 /**
2422 * Indirect draw parameters resource.
2423 */
2424 struct radv_buffer *indirect;
2425 uint64_t indirect_offset;
2426 uint32_t stride;
2427
2428 /**
2429 * Draw count parameters resource.
2430 */
2431 struct radv_buffer *count_buffer;
2432 uint64_t count_buffer_offset;
2433
2434 /**
2435 * Stream output parameters resource.
2436 */
2437 struct radv_buffer *strmout_buffer;
2438 uint64_t strmout_buffer_offset;
2439 };
2440
2441 static void
2442 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2443 const struct radv_draw_info *draw_info)
2444 {
2445 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2446 struct radv_cmd_state *state = &cmd_buffer->state;
2447 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2448 uint32_t ia_multi_vgt_param;
2449 int32_t primitive_reset_en;
2450
2451 /* Draw state. */
2452 ia_multi_vgt_param =
2453 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2454 draw_info->indirect,
2455 !!draw_info->strmout_buffer,
2456 draw_info->indirect ? 0 : draw_info->count);
2457
2458 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2459 if (info->chip_class >= GFX9) {
2460 radeon_set_uconfig_reg_idx(cs,
2461 R_030960_IA_MULTI_VGT_PARAM,
2462 4, ia_multi_vgt_param);
2463 } else if (info->chip_class >= GFX7) {
2464 radeon_set_context_reg_idx(cs,
2465 R_028AA8_IA_MULTI_VGT_PARAM,
2466 1, ia_multi_vgt_param);
2467 } else {
2468 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2469 ia_multi_vgt_param);
2470 }
2471 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2472 }
2473
2474 /* Primitive restart. */
2475 primitive_reset_en =
2476 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2477
2478 if (primitive_reset_en != state->last_primitive_reset_en) {
2479 state->last_primitive_reset_en = primitive_reset_en;
2480 if (info->chip_class >= GFX9) {
2481 radeon_set_uconfig_reg(cs,
2482 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2483 primitive_reset_en);
2484 } else {
2485 radeon_set_context_reg(cs,
2486 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2487 primitive_reset_en);
2488 }
2489 }
2490
2491 if (primitive_reset_en) {
2492 uint32_t primitive_reset_index =
2493 state->index_type ? 0xffffffffu : 0xffffu;
2494
2495 if (primitive_reset_index != state->last_primitive_reset_index) {
2496 radeon_set_context_reg(cs,
2497 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2498 primitive_reset_index);
2499 state->last_primitive_reset_index = primitive_reset_index;
2500 }
2501 }
2502
2503 if (draw_info->strmout_buffer) {
2504 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2505
2506 va += draw_info->strmout_buffer->offset +
2507 draw_info->strmout_buffer_offset;
2508
2509 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2510 draw_info->stride);
2511
2512 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2513 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2514 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2515 COPY_DATA_WR_CONFIRM);
2516 radeon_emit(cs, va);
2517 radeon_emit(cs, va >> 32);
2518 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2519 radeon_emit(cs, 0); /* unused */
2520
2521 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2522 }
2523 }
2524
2525 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2526 VkPipelineStageFlags src_stage_mask)
2527 {
2528 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2529 VK_PIPELINE_STAGE_TRANSFER_BIT |
2530 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2531 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2532 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2533 }
2534
2535 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2536 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2537 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2538 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2539 VK_PIPELINE_STAGE_TRANSFER_BIT |
2540 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2541 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2542 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2543 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2544 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2545 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2546 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2547 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2548 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2549 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2550 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2551 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2552 }
2553 }
2554
2555 static enum radv_cmd_flush_bits
2556 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2557 VkAccessFlags src_flags,
2558 struct radv_image *image)
2559 {
2560 bool flush_CB_meta = true, flush_DB_meta = true;
2561 enum radv_cmd_flush_bits flush_bits = 0;
2562 uint32_t b;
2563
2564 if (image) {
2565 if (!radv_image_has_CB_metadata(image))
2566 flush_CB_meta = false;
2567 if (!radv_image_has_htile(image))
2568 flush_DB_meta = false;
2569 }
2570
2571 for_each_bit(b, src_flags) {
2572 switch ((VkAccessFlagBits)(1 << b)) {
2573 case VK_ACCESS_SHADER_WRITE_BIT:
2574 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2575 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2576 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2577 break;
2578 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2579 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2580 if (flush_CB_meta)
2581 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2582 break;
2583 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2584 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2585 if (flush_DB_meta)
2586 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2587 break;
2588 case VK_ACCESS_TRANSFER_WRITE_BIT:
2589 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2590 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2591 RADV_CMD_FLAG_INV_GLOBAL_L2;
2592
2593 if (flush_CB_meta)
2594 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2595 if (flush_DB_meta)
2596 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2597 break;
2598 default:
2599 break;
2600 }
2601 }
2602 return flush_bits;
2603 }
2604
2605 static enum radv_cmd_flush_bits
2606 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2607 VkAccessFlags dst_flags,
2608 struct radv_image *image)
2609 {
2610 bool flush_CB_meta = true, flush_DB_meta = true;
2611 enum radv_cmd_flush_bits flush_bits = 0;
2612 bool flush_CB = true, flush_DB = true;
2613 bool image_is_coherent = false;
2614 uint32_t b;
2615
2616 if (image) {
2617 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2618 flush_CB = false;
2619 flush_DB = false;
2620 }
2621
2622 if (!radv_image_has_CB_metadata(image))
2623 flush_CB_meta = false;
2624 if (!radv_image_has_htile(image))
2625 flush_DB_meta = false;
2626
2627 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2628 if (image->info.samples == 1 &&
2629 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2630 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2631 !vk_format_is_stencil(image->vk_format)) {
2632 /* Single-sample color and single-sample depth
2633 * (not stencil) are coherent with shaders on
2634 * GFX9.
2635 */
2636 image_is_coherent = true;
2637 }
2638 }
2639 }
2640
2641 for_each_bit(b, dst_flags) {
2642 switch ((VkAccessFlagBits)(1 << b)) {
2643 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2644 case VK_ACCESS_INDEX_READ_BIT:
2645 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2646 break;
2647 case VK_ACCESS_UNIFORM_READ_BIT:
2648 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2649 break;
2650 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2651 case VK_ACCESS_TRANSFER_READ_BIT:
2652 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2653 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2654 RADV_CMD_FLAG_INV_GLOBAL_L2;
2655 break;
2656 case VK_ACCESS_SHADER_READ_BIT:
2657 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2658
2659 if (!image_is_coherent)
2660 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2661 break;
2662 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2663 if (flush_CB)
2664 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2665 if (flush_CB_meta)
2666 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2667 break;
2668 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2669 if (flush_DB)
2670 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2671 if (flush_DB_meta)
2672 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2673 break;
2674 default:
2675 break;
2676 }
2677 }
2678 return flush_bits;
2679 }
2680
2681 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2682 const struct radv_subpass_barrier *barrier)
2683 {
2684 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2685 NULL);
2686 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2687 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2688 NULL);
2689 }
2690
2691 uint32_t
2692 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2693 {
2694 struct radv_cmd_state *state = &cmd_buffer->state;
2695 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2696
2697 /* The id of this subpass shouldn't exceed the number of subpasses in
2698 * this render pass minus 1.
2699 */
2700 assert(subpass_id < state->pass->subpass_count);
2701 return subpass_id;
2702 }
2703
2704 static struct radv_sample_locations_state *
2705 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2706 uint32_t att_idx,
2707 bool begin_subpass)
2708 {
2709 struct radv_cmd_state *state = &cmd_buffer->state;
2710 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2711 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2712
2713 if (view->image->info.samples == 1)
2714 return NULL;
2715
2716 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2717 /* Return the initial sample locations if this is the initial
2718 * layout transition of the given subpass attachemnt.
2719 */
2720 if (state->attachments[att_idx].sample_location.count > 0)
2721 return &state->attachments[att_idx].sample_location;
2722 } else {
2723 /* Otherwise return the subpass sample locations if defined. */
2724 if (state->subpass_sample_locs) {
2725 /* Because the driver sets the current subpass before
2726 * initial layout transitions, we should use the sample
2727 * locations from the previous subpass to avoid an
2728 * off-by-one problem. Otherwise, use the sample
2729 * locations for the current subpass for final layout
2730 * transitions.
2731 */
2732 if (begin_subpass)
2733 subpass_id--;
2734
2735 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2736 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2737 return &state->subpass_sample_locs[i].sample_location;
2738 }
2739 }
2740 }
2741
2742 return NULL;
2743 }
2744
2745 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2746 struct radv_subpass_attachment att,
2747 bool begin_subpass)
2748 {
2749 unsigned idx = att.attachment;
2750 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2751 struct radv_sample_locations_state *sample_locs;
2752 VkImageSubresourceRange range;
2753 range.aspectMask = 0;
2754 range.baseMipLevel = view->base_mip;
2755 range.levelCount = 1;
2756 range.baseArrayLayer = view->base_layer;
2757 range.layerCount = cmd_buffer->state.framebuffer->layers;
2758
2759 if (cmd_buffer->state.subpass->view_mask) {
2760 /* If the current subpass uses multiview, the driver might have
2761 * performed a fast color/depth clear to the whole image
2762 * (including all layers). To make sure the driver will
2763 * decompress the image correctly (if needed), we have to
2764 * account for the "real" number of layers. If the view mask is
2765 * sparse, this will decompress more layers than needed.
2766 */
2767 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2768 }
2769
2770 /* Get the subpass sample locations for the given attachment, if NULL
2771 * is returned the driver will use the default HW locations.
2772 */
2773 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2774 begin_subpass);
2775
2776 radv_handle_image_transition(cmd_buffer,
2777 view->image,
2778 cmd_buffer->state.attachments[idx].current_layout,
2779 att.layout, 0, 0, &range, sample_locs);
2780
2781 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2782
2783
2784 }
2785
2786 void
2787 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2788 const struct radv_subpass *subpass)
2789 {
2790 cmd_buffer->state.subpass = subpass;
2791
2792 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2793 }
2794
2795 static VkResult
2796 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2797 struct radv_render_pass *pass,
2798 const VkRenderPassBeginInfo *info)
2799 {
2800 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2801 vk_find_struct_const(info->pNext,
2802 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2803 struct radv_cmd_state *state = &cmd_buffer->state;
2804 struct radv_framebuffer *framebuffer = state->framebuffer;
2805
2806 if (!sample_locs) {
2807 state->subpass_sample_locs = NULL;
2808 return VK_SUCCESS;
2809 }
2810
2811 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2812 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2813 &sample_locs->pAttachmentInitialSampleLocations[i];
2814 uint32_t att_idx = att_sample_locs->attachmentIndex;
2815 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2816 struct radv_image *image = att->attachment->image;
2817
2818 assert(vk_format_is_depth_or_stencil(image->vk_format));
2819
2820 /* From the Vulkan spec 1.1.108:
2821 *
2822 * "If the image referenced by the framebuffer attachment at
2823 * index attachmentIndex was not created with
2824 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2825 * then the values specified in sampleLocationsInfo are
2826 * ignored."
2827 */
2828 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2829 continue;
2830
2831 const VkSampleLocationsInfoEXT *sample_locs_info =
2832 &att_sample_locs->sampleLocationsInfo;
2833
2834 state->attachments[att_idx].sample_location.per_pixel =
2835 sample_locs_info->sampleLocationsPerPixel;
2836 state->attachments[att_idx].sample_location.grid_size =
2837 sample_locs_info->sampleLocationGridSize;
2838 state->attachments[att_idx].sample_location.count =
2839 sample_locs_info->sampleLocationsCount;
2840 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2841 sample_locs_info->pSampleLocations,
2842 sample_locs_info->sampleLocationsCount);
2843 }
2844
2845 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2846 sample_locs->postSubpassSampleLocationsCount *
2847 sizeof(state->subpass_sample_locs[0]),
2848 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2849 if (state->subpass_sample_locs == NULL) {
2850 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2851 return cmd_buffer->record_result;
2852 }
2853
2854 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2855
2856 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2857 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2858 &sample_locs->pPostSubpassSampleLocations[i];
2859 const VkSampleLocationsInfoEXT *sample_locs_info =
2860 &subpass_sample_locs_info->sampleLocationsInfo;
2861
2862 state->subpass_sample_locs[i].subpass_idx =
2863 subpass_sample_locs_info->subpassIndex;
2864 state->subpass_sample_locs[i].sample_location.per_pixel =
2865 sample_locs_info->sampleLocationsPerPixel;
2866 state->subpass_sample_locs[i].sample_location.grid_size =
2867 sample_locs_info->sampleLocationGridSize;
2868 state->subpass_sample_locs[i].sample_location.count =
2869 sample_locs_info->sampleLocationsCount;
2870 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2871 sample_locs_info->pSampleLocations,
2872 sample_locs_info->sampleLocationsCount);
2873 }
2874
2875 return VK_SUCCESS;
2876 }
2877
2878 static VkResult
2879 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2880 struct radv_render_pass *pass,
2881 const VkRenderPassBeginInfo *info)
2882 {
2883 struct radv_cmd_state *state = &cmd_buffer->state;
2884
2885 if (pass->attachment_count == 0) {
2886 state->attachments = NULL;
2887 return VK_SUCCESS;
2888 }
2889
2890 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2891 pass->attachment_count *
2892 sizeof(state->attachments[0]),
2893 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2894 if (state->attachments == NULL) {
2895 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2896 return cmd_buffer->record_result;
2897 }
2898
2899 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2900 struct radv_render_pass_attachment *att = &pass->attachments[i];
2901 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2902 VkImageAspectFlags clear_aspects = 0;
2903
2904 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2905 /* color attachment */
2906 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2907 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2908 }
2909 } else {
2910 /* depthstencil attachment */
2911 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2912 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2913 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2914 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2915 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2916 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2917 }
2918 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2919 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2920 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2921 }
2922 }
2923
2924 state->attachments[i].pending_clear_aspects = clear_aspects;
2925 state->attachments[i].cleared_views = 0;
2926 if (clear_aspects && info) {
2927 assert(info->clearValueCount > i);
2928 state->attachments[i].clear_value = info->pClearValues[i];
2929 }
2930
2931 state->attachments[i].current_layout = att->initial_layout;
2932 state->attachments[i].sample_location.count = 0;
2933 }
2934
2935 return VK_SUCCESS;
2936 }
2937
2938 VkResult radv_AllocateCommandBuffers(
2939 VkDevice _device,
2940 const VkCommandBufferAllocateInfo *pAllocateInfo,
2941 VkCommandBuffer *pCommandBuffers)
2942 {
2943 RADV_FROM_HANDLE(radv_device, device, _device);
2944 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2945
2946 VkResult result = VK_SUCCESS;
2947 uint32_t i;
2948
2949 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2950
2951 if (!list_empty(&pool->free_cmd_buffers)) {
2952 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2953
2954 list_del(&cmd_buffer->pool_link);
2955 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2956
2957 result = radv_reset_cmd_buffer(cmd_buffer);
2958 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2959 cmd_buffer->level = pAllocateInfo->level;
2960
2961 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2962 } else {
2963 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2964 &pCommandBuffers[i]);
2965 }
2966 if (result != VK_SUCCESS)
2967 break;
2968 }
2969
2970 if (result != VK_SUCCESS) {
2971 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2972 i, pCommandBuffers);
2973
2974 /* From the Vulkan 1.0.66 spec:
2975 *
2976 * "vkAllocateCommandBuffers can be used to create multiple
2977 * command buffers. If the creation of any of those command
2978 * buffers fails, the implementation must destroy all
2979 * successfully created command buffer objects from this
2980 * command, set all entries of the pCommandBuffers array to
2981 * NULL and return the error."
2982 */
2983 memset(pCommandBuffers, 0,
2984 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2985 }
2986
2987 return result;
2988 }
2989
2990 void radv_FreeCommandBuffers(
2991 VkDevice device,
2992 VkCommandPool commandPool,
2993 uint32_t commandBufferCount,
2994 const VkCommandBuffer *pCommandBuffers)
2995 {
2996 for (uint32_t i = 0; i < commandBufferCount; i++) {
2997 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2998
2999 if (cmd_buffer) {
3000 if (cmd_buffer->pool) {
3001 list_del(&cmd_buffer->pool_link);
3002 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3003 } else
3004 radv_cmd_buffer_destroy(cmd_buffer);
3005
3006 }
3007 }
3008 }
3009
3010 VkResult radv_ResetCommandBuffer(
3011 VkCommandBuffer commandBuffer,
3012 VkCommandBufferResetFlags flags)
3013 {
3014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3015 return radv_reset_cmd_buffer(cmd_buffer);
3016 }
3017
3018 VkResult radv_BeginCommandBuffer(
3019 VkCommandBuffer commandBuffer,
3020 const VkCommandBufferBeginInfo *pBeginInfo)
3021 {
3022 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3023 VkResult result = VK_SUCCESS;
3024
3025 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3026 /* If the command buffer has already been resetted with
3027 * vkResetCommandBuffer, no need to do it again.
3028 */
3029 result = radv_reset_cmd_buffer(cmd_buffer);
3030 if (result != VK_SUCCESS)
3031 return result;
3032 }
3033
3034 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3035 cmd_buffer->state.last_primitive_reset_en = -1;
3036 cmd_buffer->state.last_index_type = -1;
3037 cmd_buffer->state.last_num_instances = -1;
3038 cmd_buffer->state.last_vertex_offset = -1;
3039 cmd_buffer->state.last_first_instance = -1;
3040 cmd_buffer->state.predication_type = -1;
3041 cmd_buffer->usage_flags = pBeginInfo->flags;
3042
3043 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3044 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3045 assert(pBeginInfo->pInheritanceInfo);
3046 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3047 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3048
3049 struct radv_subpass *subpass =
3050 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3051
3052 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3053 if (result != VK_SUCCESS)
3054 return result;
3055
3056 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3057 }
3058
3059 if (unlikely(cmd_buffer->device->trace_bo)) {
3060 struct radv_device *device = cmd_buffer->device;
3061
3062 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3063 device->trace_bo);
3064
3065 radv_cmd_buffer_trace_emit(cmd_buffer);
3066 }
3067
3068 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3069
3070 return result;
3071 }
3072
3073 void radv_CmdBindVertexBuffers(
3074 VkCommandBuffer commandBuffer,
3075 uint32_t firstBinding,
3076 uint32_t bindingCount,
3077 const VkBuffer* pBuffers,
3078 const VkDeviceSize* pOffsets)
3079 {
3080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3081 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3082 bool changed = false;
3083
3084 /* We have to defer setting up vertex buffer since we need the buffer
3085 * stride from the pipeline. */
3086
3087 assert(firstBinding + bindingCount <= MAX_VBS);
3088 for (uint32_t i = 0; i < bindingCount; i++) {
3089 uint32_t idx = firstBinding + i;
3090
3091 if (!changed &&
3092 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3093 vb[idx].offset != pOffsets[i])) {
3094 changed = true;
3095 }
3096
3097 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3098 vb[idx].offset = pOffsets[i];
3099
3100 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3101 vb[idx].buffer->bo);
3102 }
3103
3104 if (!changed) {
3105 /* No state changes. */
3106 return;
3107 }
3108
3109 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3110 }
3111
3112 void radv_CmdBindIndexBuffer(
3113 VkCommandBuffer commandBuffer,
3114 VkBuffer buffer,
3115 VkDeviceSize offset,
3116 VkIndexType indexType)
3117 {
3118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3119 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3120
3121 if (cmd_buffer->state.index_buffer == index_buffer &&
3122 cmd_buffer->state.index_offset == offset &&
3123 cmd_buffer->state.index_type == indexType) {
3124 /* No state changes. */
3125 return;
3126 }
3127
3128 cmd_buffer->state.index_buffer = index_buffer;
3129 cmd_buffer->state.index_offset = offset;
3130 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3131 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3132 cmd_buffer->state.index_va += index_buffer->offset + offset;
3133
3134 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3135 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3136 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3137 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3138 }
3139
3140
3141 static void
3142 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3143 VkPipelineBindPoint bind_point,
3144 struct radv_descriptor_set *set, unsigned idx)
3145 {
3146 struct radeon_winsys *ws = cmd_buffer->device->ws;
3147
3148 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3149
3150 assert(set);
3151 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3152
3153 if (!cmd_buffer->device->use_global_bo_list) {
3154 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3155 if (set->descriptors[j])
3156 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3157 }
3158
3159 if(set->bo)
3160 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3161 }
3162
3163 void radv_CmdBindDescriptorSets(
3164 VkCommandBuffer commandBuffer,
3165 VkPipelineBindPoint pipelineBindPoint,
3166 VkPipelineLayout _layout,
3167 uint32_t firstSet,
3168 uint32_t descriptorSetCount,
3169 const VkDescriptorSet* pDescriptorSets,
3170 uint32_t dynamicOffsetCount,
3171 const uint32_t* pDynamicOffsets)
3172 {
3173 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3174 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3175 unsigned dyn_idx = 0;
3176
3177 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3178 struct radv_descriptor_state *descriptors_state =
3179 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3180
3181 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3182 unsigned idx = i + firstSet;
3183 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3184 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3185
3186 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3187 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3188 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3189 assert(dyn_idx < dynamicOffsetCount);
3190
3191 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3192 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3193 dst[0] = va;
3194 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3195 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3196 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3197 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3198 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3199 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3200 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3201 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3202 cmd_buffer->push_constant_stages |=
3203 set->layout->dynamic_shader_stages;
3204 }
3205 }
3206 }
3207
3208 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3209 struct radv_descriptor_set *set,
3210 struct radv_descriptor_set_layout *layout,
3211 VkPipelineBindPoint bind_point)
3212 {
3213 struct radv_descriptor_state *descriptors_state =
3214 radv_get_descriptors_state(cmd_buffer, bind_point);
3215 set->size = layout->size;
3216 set->layout = layout;
3217
3218 if (descriptors_state->push_set.capacity < set->size) {
3219 size_t new_size = MAX2(set->size, 1024);
3220 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3221 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3222
3223 free(set->mapped_ptr);
3224 set->mapped_ptr = malloc(new_size);
3225
3226 if (!set->mapped_ptr) {
3227 descriptors_state->push_set.capacity = 0;
3228 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3229 return false;
3230 }
3231
3232 descriptors_state->push_set.capacity = new_size;
3233 }
3234
3235 return true;
3236 }
3237
3238 void radv_meta_push_descriptor_set(
3239 struct radv_cmd_buffer* cmd_buffer,
3240 VkPipelineBindPoint pipelineBindPoint,
3241 VkPipelineLayout _layout,
3242 uint32_t set,
3243 uint32_t descriptorWriteCount,
3244 const VkWriteDescriptorSet* pDescriptorWrites)
3245 {
3246 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3247 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3248 unsigned bo_offset;
3249
3250 assert(set == 0);
3251 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3252
3253 push_set->size = layout->set[set].layout->size;
3254 push_set->layout = layout->set[set].layout;
3255
3256 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3257 &bo_offset,
3258 (void**) &push_set->mapped_ptr))
3259 return;
3260
3261 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3262 push_set->va += bo_offset;
3263
3264 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3265 radv_descriptor_set_to_handle(push_set),
3266 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3267
3268 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3269 }
3270
3271 void radv_CmdPushDescriptorSetKHR(
3272 VkCommandBuffer commandBuffer,
3273 VkPipelineBindPoint pipelineBindPoint,
3274 VkPipelineLayout _layout,
3275 uint32_t set,
3276 uint32_t descriptorWriteCount,
3277 const VkWriteDescriptorSet* pDescriptorWrites)
3278 {
3279 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3280 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3281 struct radv_descriptor_state *descriptors_state =
3282 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3283 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3284
3285 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3286
3287 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3288 layout->set[set].layout,
3289 pipelineBindPoint))
3290 return;
3291
3292 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3293 * because it is invalid, according to Vulkan spec.
3294 */
3295 for (int i = 0; i < descriptorWriteCount; i++) {
3296 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3297 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3298 }
3299
3300 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3301 radv_descriptor_set_to_handle(push_set),
3302 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3303
3304 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3305 descriptors_state->push_dirty = true;
3306 }
3307
3308 void radv_CmdPushDescriptorSetWithTemplateKHR(
3309 VkCommandBuffer commandBuffer,
3310 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3311 VkPipelineLayout _layout,
3312 uint32_t set,
3313 const void* pData)
3314 {
3315 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3316 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3317 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3318 struct radv_descriptor_state *descriptors_state =
3319 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3320 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3321
3322 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3323
3324 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3325 layout->set[set].layout,
3326 templ->bind_point))
3327 return;
3328
3329 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3330 descriptorUpdateTemplate, pData);
3331
3332 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3333 descriptors_state->push_dirty = true;
3334 }
3335
3336 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3337 VkPipelineLayout layout,
3338 VkShaderStageFlags stageFlags,
3339 uint32_t offset,
3340 uint32_t size,
3341 const void* pValues)
3342 {
3343 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3344 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3345 cmd_buffer->push_constant_stages |= stageFlags;
3346 }
3347
3348 VkResult radv_EndCommandBuffer(
3349 VkCommandBuffer commandBuffer)
3350 {
3351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3352
3353 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3354 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3355 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3356
3357 /* Make sure to sync all pending active queries at the end of
3358 * command buffer.
3359 */
3360 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3361
3362 si_emit_cache_flush(cmd_buffer);
3363 }
3364
3365 /* Make sure CP DMA is idle at the end of IBs because the kernel
3366 * doesn't wait for it.
3367 */
3368 si_cp_dma_wait_for_idle(cmd_buffer);
3369
3370 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3371 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3372
3373 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3374 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3375
3376 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3377
3378 return cmd_buffer->record_result;
3379 }
3380
3381 static void
3382 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3383 {
3384 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3385
3386 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3387 return;
3388
3389 assert(!pipeline->ctx_cs.cdw);
3390
3391 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3392
3393 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3394 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3395
3396 cmd_buffer->compute_scratch_size_needed =
3397 MAX2(cmd_buffer->compute_scratch_size_needed,
3398 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3399
3400 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3401 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3402
3403 if (unlikely(cmd_buffer->device->trace_bo))
3404 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3405 }
3406
3407 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3408 VkPipelineBindPoint bind_point)
3409 {
3410 struct radv_descriptor_state *descriptors_state =
3411 radv_get_descriptors_state(cmd_buffer, bind_point);
3412
3413 descriptors_state->dirty |= descriptors_state->valid;
3414 }
3415
3416 void radv_CmdBindPipeline(
3417 VkCommandBuffer commandBuffer,
3418 VkPipelineBindPoint pipelineBindPoint,
3419 VkPipeline _pipeline)
3420 {
3421 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3422 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3423
3424 switch (pipelineBindPoint) {
3425 case VK_PIPELINE_BIND_POINT_COMPUTE:
3426 if (cmd_buffer->state.compute_pipeline == pipeline)
3427 return;
3428 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3429
3430 cmd_buffer->state.compute_pipeline = pipeline;
3431 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3432 break;
3433 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3434 if (cmd_buffer->state.pipeline == pipeline)
3435 return;
3436 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3437
3438 cmd_buffer->state.pipeline = pipeline;
3439 if (!pipeline)
3440 break;
3441
3442 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3443 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3444
3445 /* the new vertex shader might not have the same user regs */
3446 cmd_buffer->state.last_first_instance = -1;
3447 cmd_buffer->state.last_vertex_offset = -1;
3448
3449 /* Prefetch all pipeline shaders at first draw time. */
3450 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3451
3452 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3453 radv_bind_streamout_state(cmd_buffer, pipeline);
3454
3455 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3456 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3457 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3458 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3459
3460 if (radv_pipeline_has_tess(pipeline))
3461 cmd_buffer->tess_rings_needed = true;
3462 break;
3463 default:
3464 assert(!"invalid bind point");
3465 break;
3466 }
3467 }
3468
3469 void radv_CmdSetViewport(
3470 VkCommandBuffer commandBuffer,
3471 uint32_t firstViewport,
3472 uint32_t viewportCount,
3473 const VkViewport* pViewports)
3474 {
3475 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3476 struct radv_cmd_state *state = &cmd_buffer->state;
3477 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3478
3479 assert(firstViewport < MAX_VIEWPORTS);
3480 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3481
3482 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3483 pViewports, viewportCount * sizeof(*pViewports))) {
3484 return;
3485 }
3486
3487 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3488 viewportCount * sizeof(*pViewports));
3489
3490 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3491 }
3492
3493 void radv_CmdSetScissor(
3494 VkCommandBuffer commandBuffer,
3495 uint32_t firstScissor,
3496 uint32_t scissorCount,
3497 const VkRect2D* pScissors)
3498 {
3499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3500 struct radv_cmd_state *state = &cmd_buffer->state;
3501 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3502
3503 assert(firstScissor < MAX_SCISSORS);
3504 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3505
3506 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3507 scissorCount * sizeof(*pScissors))) {
3508 return;
3509 }
3510
3511 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3512 scissorCount * sizeof(*pScissors));
3513
3514 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3515 }
3516
3517 void radv_CmdSetLineWidth(
3518 VkCommandBuffer commandBuffer,
3519 float lineWidth)
3520 {
3521 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3522
3523 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3524 return;
3525
3526 cmd_buffer->state.dynamic.line_width = lineWidth;
3527 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3528 }
3529
3530 void radv_CmdSetDepthBias(
3531 VkCommandBuffer commandBuffer,
3532 float depthBiasConstantFactor,
3533 float depthBiasClamp,
3534 float depthBiasSlopeFactor)
3535 {
3536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3537 struct radv_cmd_state *state = &cmd_buffer->state;
3538
3539 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3540 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3541 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3542 return;
3543 }
3544
3545 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3546 state->dynamic.depth_bias.clamp = depthBiasClamp;
3547 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3548
3549 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3550 }
3551
3552 void radv_CmdSetBlendConstants(
3553 VkCommandBuffer commandBuffer,
3554 const float blendConstants[4])
3555 {
3556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3557 struct radv_cmd_state *state = &cmd_buffer->state;
3558
3559 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3560 return;
3561
3562 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3563
3564 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3565 }
3566
3567 void radv_CmdSetDepthBounds(
3568 VkCommandBuffer commandBuffer,
3569 float minDepthBounds,
3570 float maxDepthBounds)
3571 {
3572 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3573 struct radv_cmd_state *state = &cmd_buffer->state;
3574
3575 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3576 state->dynamic.depth_bounds.max == maxDepthBounds) {
3577 return;
3578 }
3579
3580 state->dynamic.depth_bounds.min = minDepthBounds;
3581 state->dynamic.depth_bounds.max = maxDepthBounds;
3582
3583 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3584 }
3585
3586 void radv_CmdSetStencilCompareMask(
3587 VkCommandBuffer commandBuffer,
3588 VkStencilFaceFlags faceMask,
3589 uint32_t compareMask)
3590 {
3591 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3592 struct radv_cmd_state *state = &cmd_buffer->state;
3593 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3594 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3595
3596 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3597 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3598 return;
3599 }
3600
3601 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3602 state->dynamic.stencil_compare_mask.front = compareMask;
3603 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3604 state->dynamic.stencil_compare_mask.back = compareMask;
3605
3606 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3607 }
3608
3609 void radv_CmdSetStencilWriteMask(
3610 VkCommandBuffer commandBuffer,
3611 VkStencilFaceFlags faceMask,
3612 uint32_t writeMask)
3613 {
3614 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3615 struct radv_cmd_state *state = &cmd_buffer->state;
3616 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3617 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3618
3619 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3620 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3621 return;
3622 }
3623
3624 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3625 state->dynamic.stencil_write_mask.front = writeMask;
3626 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3627 state->dynamic.stencil_write_mask.back = writeMask;
3628
3629 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3630 }
3631
3632 void radv_CmdSetStencilReference(
3633 VkCommandBuffer commandBuffer,
3634 VkStencilFaceFlags faceMask,
3635 uint32_t reference)
3636 {
3637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3638 struct radv_cmd_state *state = &cmd_buffer->state;
3639 bool front_same = state->dynamic.stencil_reference.front == reference;
3640 bool back_same = state->dynamic.stencil_reference.back == reference;
3641
3642 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3643 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3644 return;
3645 }
3646
3647 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3648 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3649 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3650 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3651
3652 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3653 }
3654
3655 void radv_CmdSetDiscardRectangleEXT(
3656 VkCommandBuffer commandBuffer,
3657 uint32_t firstDiscardRectangle,
3658 uint32_t discardRectangleCount,
3659 const VkRect2D* pDiscardRectangles)
3660 {
3661 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3662 struct radv_cmd_state *state = &cmd_buffer->state;
3663 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3664
3665 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3666 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3667
3668 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3669 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3670 return;
3671 }
3672
3673 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3674 pDiscardRectangles, discardRectangleCount);
3675
3676 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3677 }
3678
3679 void radv_CmdSetSampleLocationsEXT(
3680 VkCommandBuffer commandBuffer,
3681 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3682 {
3683 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3684 struct radv_cmd_state *state = &cmd_buffer->state;
3685
3686 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3687
3688 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3689 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3690 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3691 typed_memcpy(&state->dynamic.sample_location.locations[0],
3692 pSampleLocationsInfo->pSampleLocations,
3693 pSampleLocationsInfo->sampleLocationsCount);
3694
3695 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3696 }
3697
3698 void radv_CmdExecuteCommands(
3699 VkCommandBuffer commandBuffer,
3700 uint32_t commandBufferCount,
3701 const VkCommandBuffer* pCmdBuffers)
3702 {
3703 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3704
3705 assert(commandBufferCount > 0);
3706
3707 /* Emit pending flushes on primary prior to executing secondary */
3708 si_emit_cache_flush(primary);
3709
3710 for (uint32_t i = 0; i < commandBufferCount; i++) {
3711 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3712
3713 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3714 secondary->scratch_size_needed);
3715 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3716 secondary->compute_scratch_size_needed);
3717
3718 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3719 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3720 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3721 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3722 if (secondary->tess_rings_needed)
3723 primary->tess_rings_needed = true;
3724 if (secondary->sample_positions_needed)
3725 primary->sample_positions_needed = true;
3726
3727 if (!secondary->state.framebuffer &&
3728 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3729 /* Emit the framebuffer state from primary if secondary
3730 * has been recorded without a framebuffer, otherwise
3731 * fast color/depth clears can't work.
3732 */
3733 radv_emit_framebuffer_state(primary);
3734 }
3735
3736 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3737
3738
3739 /* When the secondary command buffer is compute only we don't
3740 * need to re-emit the current graphics pipeline.
3741 */
3742 if (secondary->state.emitted_pipeline) {
3743 primary->state.emitted_pipeline =
3744 secondary->state.emitted_pipeline;
3745 }
3746
3747 /* When the secondary command buffer is graphics only we don't
3748 * need to re-emit the current compute pipeline.
3749 */
3750 if (secondary->state.emitted_compute_pipeline) {
3751 primary->state.emitted_compute_pipeline =
3752 secondary->state.emitted_compute_pipeline;
3753 }
3754
3755 /* Only re-emit the draw packets when needed. */
3756 if (secondary->state.last_primitive_reset_en != -1) {
3757 primary->state.last_primitive_reset_en =
3758 secondary->state.last_primitive_reset_en;
3759 }
3760
3761 if (secondary->state.last_primitive_reset_index) {
3762 primary->state.last_primitive_reset_index =
3763 secondary->state.last_primitive_reset_index;
3764 }
3765
3766 if (secondary->state.last_ia_multi_vgt_param) {
3767 primary->state.last_ia_multi_vgt_param =
3768 secondary->state.last_ia_multi_vgt_param;
3769 }
3770
3771 primary->state.last_first_instance = secondary->state.last_first_instance;
3772 primary->state.last_num_instances = secondary->state.last_num_instances;
3773 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3774
3775 if (secondary->state.last_index_type != -1) {
3776 primary->state.last_index_type =
3777 secondary->state.last_index_type;
3778 }
3779 }
3780
3781 /* After executing commands from secondary buffers we have to dirty
3782 * some states.
3783 */
3784 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3785 RADV_CMD_DIRTY_INDEX_BUFFER |
3786 RADV_CMD_DIRTY_DYNAMIC_ALL;
3787 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3788 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3789 }
3790
3791 VkResult radv_CreateCommandPool(
3792 VkDevice _device,
3793 const VkCommandPoolCreateInfo* pCreateInfo,
3794 const VkAllocationCallbacks* pAllocator,
3795 VkCommandPool* pCmdPool)
3796 {
3797 RADV_FROM_HANDLE(radv_device, device, _device);
3798 struct radv_cmd_pool *pool;
3799
3800 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3801 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3802 if (pool == NULL)
3803 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3804
3805 if (pAllocator)
3806 pool->alloc = *pAllocator;
3807 else
3808 pool->alloc = device->alloc;
3809
3810 list_inithead(&pool->cmd_buffers);
3811 list_inithead(&pool->free_cmd_buffers);
3812
3813 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3814
3815 *pCmdPool = radv_cmd_pool_to_handle(pool);
3816
3817 return VK_SUCCESS;
3818
3819 }
3820
3821 void radv_DestroyCommandPool(
3822 VkDevice _device,
3823 VkCommandPool commandPool,
3824 const VkAllocationCallbacks* pAllocator)
3825 {
3826 RADV_FROM_HANDLE(radv_device, device, _device);
3827 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3828
3829 if (!pool)
3830 return;
3831
3832 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3833 &pool->cmd_buffers, pool_link) {
3834 radv_cmd_buffer_destroy(cmd_buffer);
3835 }
3836
3837 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3838 &pool->free_cmd_buffers, pool_link) {
3839 radv_cmd_buffer_destroy(cmd_buffer);
3840 }
3841
3842 vk_free2(&device->alloc, pAllocator, pool);
3843 }
3844
3845 VkResult radv_ResetCommandPool(
3846 VkDevice device,
3847 VkCommandPool commandPool,
3848 VkCommandPoolResetFlags flags)
3849 {
3850 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3851 VkResult result;
3852
3853 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3854 &pool->cmd_buffers, pool_link) {
3855 result = radv_reset_cmd_buffer(cmd_buffer);
3856 if (result != VK_SUCCESS)
3857 return result;
3858 }
3859
3860 return VK_SUCCESS;
3861 }
3862
3863 void radv_TrimCommandPool(
3864 VkDevice device,
3865 VkCommandPool commandPool,
3866 VkCommandPoolTrimFlags flags)
3867 {
3868 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3869
3870 if (!pool)
3871 return;
3872
3873 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3874 &pool->free_cmd_buffers, pool_link) {
3875 radv_cmd_buffer_destroy(cmd_buffer);
3876 }
3877 }
3878
3879 static void
3880 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3881 uint32_t subpass_id)
3882 {
3883 struct radv_cmd_state *state = &cmd_buffer->state;
3884 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3885
3886 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3887 cmd_buffer->cs, 4096);
3888
3889 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3890
3891 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3892
3893 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3894 const uint32_t a = subpass->attachments[i].attachment;
3895 if (a == VK_ATTACHMENT_UNUSED)
3896 continue;
3897
3898 radv_handle_subpass_image_transition(cmd_buffer,
3899 subpass->attachments[i],
3900 true);
3901 }
3902
3903 radv_cmd_buffer_clear_subpass(cmd_buffer);
3904
3905 assert(cmd_buffer->cs->cdw <= cdw_max);
3906 }
3907
3908 static void
3909 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3910 {
3911 struct radv_cmd_state *state = &cmd_buffer->state;
3912 const struct radv_subpass *subpass = state->subpass;
3913 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3914
3915 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3916
3917 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3918 const uint32_t a = subpass->attachments[i].attachment;
3919 if (a == VK_ATTACHMENT_UNUSED)
3920 continue;
3921
3922 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3923 continue;
3924
3925 VkImageLayout layout = state->pass->attachments[a].final_layout;
3926 struct radv_subpass_attachment att = { a, layout };
3927 radv_handle_subpass_image_transition(cmd_buffer, att, false);
3928 }
3929 }
3930
3931 void radv_CmdBeginRenderPass(
3932 VkCommandBuffer commandBuffer,
3933 const VkRenderPassBeginInfo* pRenderPassBegin,
3934 VkSubpassContents contents)
3935 {
3936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3937 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3938 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3939 VkResult result;
3940
3941 cmd_buffer->state.framebuffer = framebuffer;
3942 cmd_buffer->state.pass = pass;
3943 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3944
3945 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3946 if (result != VK_SUCCESS)
3947 return;
3948
3949 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
3950 if (result != VK_SUCCESS)
3951 return;
3952
3953 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3954 }
3955
3956 void radv_CmdBeginRenderPass2KHR(
3957 VkCommandBuffer commandBuffer,
3958 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3959 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3960 {
3961 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3962 pSubpassBeginInfo->contents);
3963 }
3964
3965 void radv_CmdNextSubpass(
3966 VkCommandBuffer commandBuffer,
3967 VkSubpassContents contents)
3968 {
3969 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3970
3971 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3972 radv_cmd_buffer_end_subpass(cmd_buffer);
3973 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3974 }
3975
3976 void radv_CmdNextSubpass2KHR(
3977 VkCommandBuffer commandBuffer,
3978 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3979 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3980 {
3981 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3982 }
3983
3984 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3985 {
3986 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3987 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3988 if (!radv_get_shader(pipeline, stage))
3989 continue;
3990
3991 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3992 if (loc->sgpr_idx == -1)
3993 continue;
3994 uint32_t base_reg = pipeline->user_data_0[stage];
3995 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3996
3997 }
3998 if (pipeline->gs_copy_shader) {
3999 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4000 if (loc->sgpr_idx != -1) {
4001 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4002 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4003 }
4004 }
4005 }
4006
4007 static void
4008 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4009 uint32_t vertex_count,
4010 bool use_opaque)
4011 {
4012 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4013 radeon_emit(cmd_buffer->cs, vertex_count);
4014 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4015 S_0287F0_USE_OPAQUE(use_opaque));
4016 }
4017
4018 static void
4019 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4020 uint64_t index_va,
4021 uint32_t index_count)
4022 {
4023 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4024 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4025 radeon_emit(cmd_buffer->cs, index_va);
4026 radeon_emit(cmd_buffer->cs, index_va >> 32);
4027 radeon_emit(cmd_buffer->cs, index_count);
4028 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4029 }
4030
4031 static void
4032 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4033 bool indexed,
4034 uint32_t draw_count,
4035 uint64_t count_va,
4036 uint32_t stride)
4037 {
4038 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4039 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4040 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4041 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4042 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4043 bool predicating = cmd_buffer->state.predicating;
4044 assert(base_reg);
4045
4046 /* just reset draw state for vertex data */
4047 cmd_buffer->state.last_first_instance = -1;
4048 cmd_buffer->state.last_num_instances = -1;
4049 cmd_buffer->state.last_vertex_offset = -1;
4050
4051 if (draw_count == 1 && !count_va && !draw_id_enable) {
4052 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4053 PKT3_DRAW_INDIRECT, 3, predicating));
4054 radeon_emit(cs, 0);
4055 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4056 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4057 radeon_emit(cs, di_src_sel);
4058 } else {
4059 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4060 PKT3_DRAW_INDIRECT_MULTI,
4061 8, predicating));
4062 radeon_emit(cs, 0);
4063 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4064 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4065 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4066 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4067 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4068 radeon_emit(cs, draw_count); /* count */
4069 radeon_emit(cs, count_va); /* count_addr */
4070 radeon_emit(cs, count_va >> 32);
4071 radeon_emit(cs, stride); /* stride */
4072 radeon_emit(cs, di_src_sel);
4073 }
4074 }
4075
4076 static void
4077 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4078 const struct radv_draw_info *info)
4079 {
4080 struct radv_cmd_state *state = &cmd_buffer->state;
4081 struct radeon_winsys *ws = cmd_buffer->device->ws;
4082 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4083
4084 if (info->indirect) {
4085 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4086 uint64_t count_va = 0;
4087
4088 va += info->indirect->offset + info->indirect_offset;
4089
4090 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4091
4092 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4093 radeon_emit(cs, 1);
4094 radeon_emit(cs, va);
4095 radeon_emit(cs, va >> 32);
4096
4097 if (info->count_buffer) {
4098 count_va = radv_buffer_get_va(info->count_buffer->bo);
4099 count_va += info->count_buffer->offset +
4100 info->count_buffer_offset;
4101
4102 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4103 }
4104
4105 if (!state->subpass->view_mask) {
4106 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4107 info->indexed,
4108 info->count,
4109 count_va,
4110 info->stride);
4111 } else {
4112 unsigned i;
4113 for_each_bit(i, state->subpass->view_mask) {
4114 radv_emit_view_index(cmd_buffer, i);
4115
4116 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4117 info->indexed,
4118 info->count,
4119 count_va,
4120 info->stride);
4121 }
4122 }
4123 } else {
4124 assert(state->pipeline->graphics.vtx_base_sgpr);
4125
4126 if (info->vertex_offset != state->last_vertex_offset ||
4127 info->first_instance != state->last_first_instance) {
4128 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4129 state->pipeline->graphics.vtx_emit_num);
4130
4131 radeon_emit(cs, info->vertex_offset);
4132 radeon_emit(cs, info->first_instance);
4133 if (state->pipeline->graphics.vtx_emit_num == 3)
4134 radeon_emit(cs, 0);
4135 state->last_first_instance = info->first_instance;
4136 state->last_vertex_offset = info->vertex_offset;
4137 }
4138
4139 if (state->last_num_instances != info->instance_count) {
4140 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4141 radeon_emit(cs, info->instance_count);
4142 state->last_num_instances = info->instance_count;
4143 }
4144
4145 if (info->indexed) {
4146 int index_size = state->index_type ? 4 : 2;
4147 uint64_t index_va;
4148
4149 index_va = state->index_va;
4150 index_va += info->first_index * index_size;
4151
4152 if (!state->subpass->view_mask) {
4153 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4154 index_va,
4155 info->count);
4156 } else {
4157 unsigned i;
4158 for_each_bit(i, state->subpass->view_mask) {
4159 radv_emit_view_index(cmd_buffer, i);
4160
4161 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4162 index_va,
4163 info->count);
4164 }
4165 }
4166 } else {
4167 if (!state->subpass->view_mask) {
4168 radv_cs_emit_draw_packet(cmd_buffer,
4169 info->count,
4170 !!info->strmout_buffer);
4171 } else {
4172 unsigned i;
4173 for_each_bit(i, state->subpass->view_mask) {
4174 radv_emit_view_index(cmd_buffer, i);
4175
4176 radv_cs_emit_draw_packet(cmd_buffer,
4177 info->count,
4178 !!info->strmout_buffer);
4179 }
4180 }
4181 }
4182 }
4183 }
4184
4185 /*
4186 * Vega and raven have a bug which triggers if there are multiple context
4187 * register contexts active at the same time with different scissor values.
4188 *
4189 * There are two possible workarounds:
4190 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4191 * there is only ever 1 active set of scissor values at the same time.
4192 *
4193 * 2) Whenever the hardware switches contexts we have to set the scissor
4194 * registers again even if it is a noop. That way the new context gets
4195 * the correct scissor values.
4196 *
4197 * This implements option 2. radv_need_late_scissor_emission needs to
4198 * return true on affected HW if radv_emit_all_graphics_states sets
4199 * any context registers.
4200 */
4201 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4202 const struct radv_draw_info *info)
4203 {
4204 struct radv_cmd_state *state = &cmd_buffer->state;
4205
4206 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4207 return false;
4208
4209 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4210 return true;
4211
4212 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4213
4214 /* Index, vertex and streamout buffers don't change context regs, and
4215 * pipeline is already handled.
4216 */
4217 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4218 RADV_CMD_DIRTY_VERTEX_BUFFER |
4219 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4220 RADV_CMD_DIRTY_PIPELINE);
4221
4222 if (cmd_buffer->state.dirty & used_states)
4223 return true;
4224
4225 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4226 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4227 return true;
4228
4229 return false;
4230 }
4231
4232 static void
4233 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4234 const struct radv_draw_info *info)
4235 {
4236 bool late_scissor_emission;
4237
4238 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4239 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4240 radv_emit_rbplus_state(cmd_buffer);
4241
4242 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4243 radv_emit_graphics_pipeline(cmd_buffer);
4244
4245 /* This should be before the cmd_buffer->state.dirty is cleared
4246 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4247 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4248 late_scissor_emission =
4249 radv_need_late_scissor_emission(cmd_buffer, info);
4250
4251 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4252 radv_emit_framebuffer_state(cmd_buffer);
4253
4254 if (info->indexed) {
4255 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4256 radv_emit_index_buffer(cmd_buffer);
4257 } else {
4258 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4259 * so the state must be re-emitted before the next indexed
4260 * draw.
4261 */
4262 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4263 cmd_buffer->state.last_index_type = -1;
4264 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4265 }
4266 }
4267
4268 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4269
4270 radv_emit_draw_registers(cmd_buffer, info);
4271
4272 if (late_scissor_emission)
4273 radv_emit_scissor(cmd_buffer);
4274 }
4275
4276 static void
4277 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4278 const struct radv_draw_info *info)
4279 {
4280 struct radeon_info *rad_info =
4281 &cmd_buffer->device->physical_device->rad_info;
4282 bool has_prefetch =
4283 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4284 bool pipeline_is_dirty =
4285 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4286 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4287
4288 MAYBE_UNUSED unsigned cdw_max =
4289 radeon_check_space(cmd_buffer->device->ws,
4290 cmd_buffer->cs, 4096);
4291
4292 if (likely(!info->indirect)) {
4293 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4294 * no workaround for indirect draws, but we can at least skip
4295 * direct draws.
4296 */
4297 if (unlikely(!info->instance_count))
4298 return;
4299
4300 /* Handle count == 0. */
4301 if (unlikely(!info->count && !info->strmout_buffer))
4302 return;
4303 }
4304
4305 /* Use optimal packet order based on whether we need to sync the
4306 * pipeline.
4307 */
4308 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4309 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4310 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4311 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4312 /* If we have to wait for idle, set all states first, so that
4313 * all SET packets are processed in parallel with previous draw
4314 * calls. Then upload descriptors, set shader pointers, and
4315 * draw, and prefetch at the end. This ensures that the time
4316 * the CUs are idle is very short. (there are only SET_SH
4317 * packets between the wait and the draw)
4318 */
4319 radv_emit_all_graphics_states(cmd_buffer, info);
4320 si_emit_cache_flush(cmd_buffer);
4321 /* <-- CUs are idle here --> */
4322
4323 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4324
4325 radv_emit_draw_packets(cmd_buffer, info);
4326 /* <-- CUs are busy here --> */
4327
4328 /* Start prefetches after the draw has been started. Both will
4329 * run in parallel, but starting the draw first is more
4330 * important.
4331 */
4332 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4333 radv_emit_prefetch_L2(cmd_buffer,
4334 cmd_buffer->state.pipeline, false);
4335 }
4336 } else {
4337 /* If we don't wait for idle, start prefetches first, then set
4338 * states, and draw at the end.
4339 */
4340 si_emit_cache_flush(cmd_buffer);
4341
4342 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4343 /* Only prefetch the vertex shader and VBO descriptors
4344 * in order to start the draw as soon as possible.
4345 */
4346 radv_emit_prefetch_L2(cmd_buffer,
4347 cmd_buffer->state.pipeline, true);
4348 }
4349
4350 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4351
4352 radv_emit_all_graphics_states(cmd_buffer, info);
4353 radv_emit_draw_packets(cmd_buffer, info);
4354
4355 /* Prefetch the remaining shaders after the draw has been
4356 * started.
4357 */
4358 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4359 radv_emit_prefetch_L2(cmd_buffer,
4360 cmd_buffer->state.pipeline, false);
4361 }
4362 }
4363
4364 /* Workaround for a VGT hang when streamout is enabled.
4365 * It must be done after drawing.
4366 */
4367 if (cmd_buffer->state.streamout.streamout_enabled &&
4368 (rad_info->family == CHIP_HAWAII ||
4369 rad_info->family == CHIP_TONGA ||
4370 rad_info->family == CHIP_FIJI)) {
4371 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4372 }
4373
4374 assert(cmd_buffer->cs->cdw <= cdw_max);
4375 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4376 }
4377
4378 void radv_CmdDraw(
4379 VkCommandBuffer commandBuffer,
4380 uint32_t vertexCount,
4381 uint32_t instanceCount,
4382 uint32_t firstVertex,
4383 uint32_t firstInstance)
4384 {
4385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4386 struct radv_draw_info info = {};
4387
4388 info.count = vertexCount;
4389 info.instance_count = instanceCount;
4390 info.first_instance = firstInstance;
4391 info.vertex_offset = firstVertex;
4392
4393 radv_draw(cmd_buffer, &info);
4394 }
4395
4396 void radv_CmdDrawIndexed(
4397 VkCommandBuffer commandBuffer,
4398 uint32_t indexCount,
4399 uint32_t instanceCount,
4400 uint32_t firstIndex,
4401 int32_t vertexOffset,
4402 uint32_t firstInstance)
4403 {
4404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4405 struct radv_draw_info info = {};
4406
4407 info.indexed = true;
4408 info.count = indexCount;
4409 info.instance_count = instanceCount;
4410 info.first_index = firstIndex;
4411 info.vertex_offset = vertexOffset;
4412 info.first_instance = firstInstance;
4413
4414 radv_draw(cmd_buffer, &info);
4415 }
4416
4417 void radv_CmdDrawIndirect(
4418 VkCommandBuffer commandBuffer,
4419 VkBuffer _buffer,
4420 VkDeviceSize offset,
4421 uint32_t drawCount,
4422 uint32_t stride)
4423 {
4424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4425 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4426 struct radv_draw_info info = {};
4427
4428 info.count = drawCount;
4429 info.indirect = buffer;
4430 info.indirect_offset = offset;
4431 info.stride = stride;
4432
4433 radv_draw(cmd_buffer, &info);
4434 }
4435
4436 void radv_CmdDrawIndexedIndirect(
4437 VkCommandBuffer commandBuffer,
4438 VkBuffer _buffer,
4439 VkDeviceSize offset,
4440 uint32_t drawCount,
4441 uint32_t stride)
4442 {
4443 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4444 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4445 struct radv_draw_info info = {};
4446
4447 info.indexed = true;
4448 info.count = drawCount;
4449 info.indirect = buffer;
4450 info.indirect_offset = offset;
4451 info.stride = stride;
4452
4453 radv_draw(cmd_buffer, &info);
4454 }
4455
4456 void radv_CmdDrawIndirectCountKHR(
4457 VkCommandBuffer commandBuffer,
4458 VkBuffer _buffer,
4459 VkDeviceSize offset,
4460 VkBuffer _countBuffer,
4461 VkDeviceSize countBufferOffset,
4462 uint32_t maxDrawCount,
4463 uint32_t stride)
4464 {
4465 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4466 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4467 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4468 struct radv_draw_info info = {};
4469
4470 info.count = maxDrawCount;
4471 info.indirect = buffer;
4472 info.indirect_offset = offset;
4473 info.count_buffer = count_buffer;
4474 info.count_buffer_offset = countBufferOffset;
4475 info.stride = stride;
4476
4477 radv_draw(cmd_buffer, &info);
4478 }
4479
4480 void radv_CmdDrawIndexedIndirectCountKHR(
4481 VkCommandBuffer commandBuffer,
4482 VkBuffer _buffer,
4483 VkDeviceSize offset,
4484 VkBuffer _countBuffer,
4485 VkDeviceSize countBufferOffset,
4486 uint32_t maxDrawCount,
4487 uint32_t stride)
4488 {
4489 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4490 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4491 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4492 struct radv_draw_info info = {};
4493
4494 info.indexed = true;
4495 info.count = maxDrawCount;
4496 info.indirect = buffer;
4497 info.indirect_offset = offset;
4498 info.count_buffer = count_buffer;
4499 info.count_buffer_offset = countBufferOffset;
4500 info.stride = stride;
4501
4502 radv_draw(cmd_buffer, &info);
4503 }
4504
4505 struct radv_dispatch_info {
4506 /**
4507 * Determine the layout of the grid (in block units) to be used.
4508 */
4509 uint32_t blocks[3];
4510
4511 /**
4512 * A starting offset for the grid. If unaligned is set, the offset
4513 * must still be aligned.
4514 */
4515 uint32_t offsets[3];
4516 /**
4517 * Whether it's an unaligned compute dispatch.
4518 */
4519 bool unaligned;
4520
4521 /**
4522 * Indirect compute parameters resource.
4523 */
4524 struct radv_buffer *indirect;
4525 uint64_t indirect_offset;
4526 };
4527
4528 static void
4529 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4530 const struct radv_dispatch_info *info)
4531 {
4532 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4533 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4534 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4535 struct radeon_winsys *ws = cmd_buffer->device->ws;
4536 bool predicating = cmd_buffer->state.predicating;
4537 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4538 struct radv_userdata_info *loc;
4539
4540 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4541 AC_UD_CS_GRID_SIZE);
4542
4543 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4544
4545 if (info->indirect) {
4546 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4547
4548 va += info->indirect->offset + info->indirect_offset;
4549
4550 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4551
4552 if (loc->sgpr_idx != -1) {
4553 for (unsigned i = 0; i < 3; ++i) {
4554 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4555 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4556 COPY_DATA_DST_SEL(COPY_DATA_REG));
4557 radeon_emit(cs, (va + 4 * i));
4558 radeon_emit(cs, (va + 4 * i) >> 32);
4559 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4560 + loc->sgpr_idx * 4) >> 2) + i);
4561 radeon_emit(cs, 0);
4562 }
4563 }
4564
4565 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4566 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4567 PKT3_SHADER_TYPE_S(1));
4568 radeon_emit(cs, va);
4569 radeon_emit(cs, va >> 32);
4570 radeon_emit(cs, dispatch_initiator);
4571 } else {
4572 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4573 PKT3_SHADER_TYPE_S(1));
4574 radeon_emit(cs, 1);
4575 radeon_emit(cs, va);
4576 radeon_emit(cs, va >> 32);
4577
4578 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4579 PKT3_SHADER_TYPE_S(1));
4580 radeon_emit(cs, 0);
4581 radeon_emit(cs, dispatch_initiator);
4582 }
4583 } else {
4584 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4585 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4586
4587 if (info->unaligned) {
4588 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4589 unsigned remainder[3];
4590
4591 /* If aligned, these should be an entire block size,
4592 * not 0.
4593 */
4594 remainder[0] = blocks[0] + cs_block_size[0] -
4595 align_u32_npot(blocks[0], cs_block_size[0]);
4596 remainder[1] = blocks[1] + cs_block_size[1] -
4597 align_u32_npot(blocks[1], cs_block_size[1]);
4598 remainder[2] = blocks[2] + cs_block_size[2] -
4599 align_u32_npot(blocks[2], cs_block_size[2]);
4600
4601 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4602 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4603 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4604
4605 for(unsigned i = 0; i < 3; ++i) {
4606 assert(offsets[i] % cs_block_size[i] == 0);
4607 offsets[i] /= cs_block_size[i];
4608 }
4609
4610 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4611 radeon_emit(cs,
4612 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4613 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4614 radeon_emit(cs,
4615 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4616 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4617 radeon_emit(cs,
4618 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4619 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4620
4621 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4622 }
4623
4624 if (loc->sgpr_idx != -1) {
4625 assert(loc->num_sgprs == 3);
4626
4627 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4628 loc->sgpr_idx * 4, 3);
4629 radeon_emit(cs, blocks[0]);
4630 radeon_emit(cs, blocks[1]);
4631 radeon_emit(cs, blocks[2]);
4632 }
4633
4634 if (offsets[0] || offsets[1] || offsets[2]) {
4635 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4636 radeon_emit(cs, offsets[0]);
4637 radeon_emit(cs, offsets[1]);
4638 radeon_emit(cs, offsets[2]);
4639
4640 /* The blocks in the packet are not counts but end values. */
4641 for (unsigned i = 0; i < 3; ++i)
4642 blocks[i] += offsets[i];
4643 } else {
4644 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4645 }
4646
4647 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4648 PKT3_SHADER_TYPE_S(1));
4649 radeon_emit(cs, blocks[0]);
4650 radeon_emit(cs, blocks[1]);
4651 radeon_emit(cs, blocks[2]);
4652 radeon_emit(cs, dispatch_initiator);
4653 }
4654
4655 assert(cmd_buffer->cs->cdw <= cdw_max);
4656 }
4657
4658 static void
4659 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4660 {
4661 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4662 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4663 }
4664
4665 static void
4666 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4667 const struct radv_dispatch_info *info)
4668 {
4669 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4670 bool has_prefetch =
4671 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4672 bool pipeline_is_dirty = pipeline &&
4673 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4674
4675 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4676 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4677 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4678 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4679 /* If we have to wait for idle, set all states first, so that
4680 * all SET packets are processed in parallel with previous draw
4681 * calls. Then upload descriptors, set shader pointers, and
4682 * dispatch, and prefetch at the end. This ensures that the
4683 * time the CUs are idle is very short. (there are only SET_SH
4684 * packets between the wait and the draw)
4685 */
4686 radv_emit_compute_pipeline(cmd_buffer);
4687 si_emit_cache_flush(cmd_buffer);
4688 /* <-- CUs are idle here --> */
4689
4690 radv_upload_compute_shader_descriptors(cmd_buffer);
4691
4692 radv_emit_dispatch_packets(cmd_buffer, info);
4693 /* <-- CUs are busy here --> */
4694
4695 /* Start prefetches after the dispatch has been started. Both
4696 * will run in parallel, but starting the dispatch first is
4697 * more important.
4698 */
4699 if (has_prefetch && pipeline_is_dirty) {
4700 radv_emit_shader_prefetch(cmd_buffer,
4701 pipeline->shaders[MESA_SHADER_COMPUTE]);
4702 }
4703 } else {
4704 /* If we don't wait for idle, start prefetches first, then set
4705 * states, and dispatch at the end.
4706 */
4707 si_emit_cache_flush(cmd_buffer);
4708
4709 if (has_prefetch && pipeline_is_dirty) {
4710 radv_emit_shader_prefetch(cmd_buffer,
4711 pipeline->shaders[MESA_SHADER_COMPUTE]);
4712 }
4713
4714 radv_upload_compute_shader_descriptors(cmd_buffer);
4715
4716 radv_emit_compute_pipeline(cmd_buffer);
4717 radv_emit_dispatch_packets(cmd_buffer, info);
4718 }
4719
4720 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4721 }
4722
4723 void radv_CmdDispatchBase(
4724 VkCommandBuffer commandBuffer,
4725 uint32_t base_x,
4726 uint32_t base_y,
4727 uint32_t base_z,
4728 uint32_t x,
4729 uint32_t y,
4730 uint32_t z)
4731 {
4732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4733 struct radv_dispatch_info info = {};
4734
4735 info.blocks[0] = x;
4736 info.blocks[1] = y;
4737 info.blocks[2] = z;
4738
4739 info.offsets[0] = base_x;
4740 info.offsets[1] = base_y;
4741 info.offsets[2] = base_z;
4742 radv_dispatch(cmd_buffer, &info);
4743 }
4744
4745 void radv_CmdDispatch(
4746 VkCommandBuffer commandBuffer,
4747 uint32_t x,
4748 uint32_t y,
4749 uint32_t z)
4750 {
4751 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4752 }
4753
4754 void radv_CmdDispatchIndirect(
4755 VkCommandBuffer commandBuffer,
4756 VkBuffer _buffer,
4757 VkDeviceSize offset)
4758 {
4759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4760 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4761 struct radv_dispatch_info info = {};
4762
4763 info.indirect = buffer;
4764 info.indirect_offset = offset;
4765
4766 radv_dispatch(cmd_buffer, &info);
4767 }
4768
4769 void radv_unaligned_dispatch(
4770 struct radv_cmd_buffer *cmd_buffer,
4771 uint32_t x,
4772 uint32_t y,
4773 uint32_t z)
4774 {
4775 struct radv_dispatch_info info = {};
4776
4777 info.blocks[0] = x;
4778 info.blocks[1] = y;
4779 info.blocks[2] = z;
4780 info.unaligned = 1;
4781
4782 radv_dispatch(cmd_buffer, &info);
4783 }
4784
4785 void radv_CmdEndRenderPass(
4786 VkCommandBuffer commandBuffer)
4787 {
4788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4789
4790 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4791
4792 radv_cmd_buffer_end_subpass(cmd_buffer);
4793
4794 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4795 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4796
4797 cmd_buffer->state.pass = NULL;
4798 cmd_buffer->state.subpass = NULL;
4799 cmd_buffer->state.attachments = NULL;
4800 cmd_buffer->state.framebuffer = NULL;
4801 cmd_buffer->state.subpass_sample_locs = NULL;
4802 }
4803
4804 void radv_CmdEndRenderPass2KHR(
4805 VkCommandBuffer commandBuffer,
4806 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4807 {
4808 radv_CmdEndRenderPass(commandBuffer);
4809 }
4810
4811 /*
4812 * For HTILE we have the following interesting clear words:
4813 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4814 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4815 * 0xfffffff0: Clear depth to 1.0
4816 * 0x00000000: Clear depth to 0.0
4817 */
4818 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4819 struct radv_image *image,
4820 const VkImageSubresourceRange *range,
4821 uint32_t clear_word)
4822 {
4823 assert(range->baseMipLevel == 0);
4824 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4825 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4826 struct radv_cmd_state *state = &cmd_buffer->state;
4827 VkClearDepthStencilValue value = {};
4828
4829 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4830 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4831
4832 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4833
4834 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4835
4836 if (vk_format_is_stencil(image->vk_format))
4837 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4838
4839 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4840
4841 if (radv_image_is_tc_compat_htile(image)) {
4842 /* Initialize the TC-compat metada value to 0 because by
4843 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4844 * need have to conditionally update its value when performing
4845 * a fast depth clear.
4846 */
4847 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4848 }
4849 }
4850
4851 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4852 struct radv_image *image,
4853 VkImageLayout src_layout,
4854 VkImageLayout dst_layout,
4855 unsigned src_queue_mask,
4856 unsigned dst_queue_mask,
4857 const VkImageSubresourceRange *range,
4858 struct radv_sample_locations_state *sample_locs)
4859 {
4860 if (!radv_image_has_htile(image))
4861 return;
4862
4863 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4864 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4865
4866 if (radv_layout_is_htile_compressed(image, dst_layout,
4867 dst_queue_mask)) {
4868 clear_value = 0;
4869 }
4870
4871 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4872 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4873 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4874 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4875 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4876 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4877 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4878 VkImageSubresourceRange local_range = *range;
4879 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4880 local_range.baseMipLevel = 0;
4881 local_range.levelCount = 1;
4882
4883 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4884 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4885
4886 radv_decompress_depth_image_inplace(cmd_buffer, image,
4887 &local_range, sample_locs);
4888
4889 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4890 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4891 }
4892 }
4893
4894 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4895 struct radv_image *image, uint32_t value)
4896 {
4897 struct radv_cmd_state *state = &cmd_buffer->state;
4898
4899 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4900 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4901
4902 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4903
4904 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4905 }
4906
4907 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4908 struct radv_image *image,
4909 const VkImageSubresourceRange *range)
4910 {
4911 struct radv_cmd_state *state = &cmd_buffer->state;
4912 static const uint32_t fmask_clear_values[4] = {
4913 0x00000000,
4914 0x02020202,
4915 0xE4E4E4E4,
4916 0x76543210
4917 };
4918 uint32_t log2_samples = util_logbase2(image->info.samples);
4919 uint32_t value = fmask_clear_values[log2_samples];
4920
4921 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4922 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4923
4924 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
4925
4926 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4927 }
4928
4929 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4930 struct radv_image *image,
4931 const VkImageSubresourceRange *range, uint32_t value)
4932 {
4933 struct radv_cmd_state *state = &cmd_buffer->state;
4934 uint32_t level_count = radv_get_levelCount(image, range);
4935 unsigned size = 0;
4936
4937 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4938 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4939
4940 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
4941 /* Mipmap level aren't implemented. */
4942 assert(level_count == 1);
4943 state->flush_bits |= radv_clear_dcc(cmd_buffer, image,
4944 range, value);
4945 } else {
4946 /* Initialize the mipmap levels with DCC first. */
4947 for (unsigned l = 0; l < level_count; l++) {
4948 uint32_t level = range->baseMipLevel + l;
4949 struct legacy_surf_level *surf_level =
4950 &image->planes[0].surface.u.legacy.level[level];
4951
4952 if (!surf_level->dcc_fast_clear_size)
4953 break;
4954
4955 state->flush_bits |=
4956 radv_dcc_clear_level(cmd_buffer, image,
4957 level, value);
4958 }
4959
4960 /* When DCC is enabled with mipmaps, some levels might not
4961 * support fast clears and we have to initialize them as "fully
4962 * expanded".
4963 */
4964 /* Compute the size of all fast clearable DCC levels. */
4965 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
4966 struct legacy_surf_level *surf_level =
4967 &image->planes[0].surface.u.legacy.level[i];
4968
4969 if (!surf_level->dcc_fast_clear_size)
4970 break;
4971
4972 size = surf_level->dcc_offset + surf_level->dcc_fast_clear_size;
4973 }
4974
4975 /* Initialize the mipmap levels without DCC. */
4976 if (size != image->planes[0].surface.dcc_size) {
4977 state->flush_bits |=
4978 radv_fill_buffer(cmd_buffer, image->bo,
4979 image->offset + image->dcc_offset + size,
4980 image->planes[0].surface.dcc_size - size,
4981 0xffffffff);
4982 }
4983 }
4984
4985 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4986 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4987 }
4988
4989 /**
4990 * Initialize DCC/FMASK/CMASK metadata for a color image.
4991 */
4992 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4993 struct radv_image *image,
4994 VkImageLayout src_layout,
4995 VkImageLayout dst_layout,
4996 unsigned src_queue_mask,
4997 unsigned dst_queue_mask,
4998 const VkImageSubresourceRange *range)
4999 {
5000 if (radv_image_has_cmask(image)) {
5001 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5002
5003 /* TODO: clarify this. */
5004 if (radv_image_has_fmask(image)) {
5005 value = 0xccccccccu;
5006 }
5007
5008 radv_initialise_cmask(cmd_buffer, image, value);
5009 }
5010
5011 if (radv_image_has_fmask(image)) {
5012 radv_initialize_fmask(cmd_buffer, image, range);
5013 }
5014
5015 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5016 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5017 bool need_decompress_pass = false;
5018
5019 if (radv_layout_dcc_compressed(image, dst_layout,
5020 dst_queue_mask)) {
5021 value = 0x20202020u;
5022 need_decompress_pass = true;
5023 }
5024
5025 radv_initialize_dcc(cmd_buffer, image, range, value);
5026
5027 radv_update_fce_metadata(cmd_buffer, image, range,
5028 need_decompress_pass);
5029 }
5030
5031 if (radv_image_has_cmask(image) ||
5032 radv_dcc_enabled(image, range->baseMipLevel)) {
5033 uint32_t color_values[2] = {};
5034 radv_set_color_clear_metadata(cmd_buffer, image, range,
5035 color_values);
5036 }
5037 }
5038
5039 /**
5040 * Handle color image transitions for DCC/FMASK/CMASK.
5041 */
5042 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5043 struct radv_image *image,
5044 VkImageLayout src_layout,
5045 VkImageLayout dst_layout,
5046 unsigned src_queue_mask,
5047 unsigned dst_queue_mask,
5048 const VkImageSubresourceRange *range)
5049 {
5050 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5051 radv_init_color_image_metadata(cmd_buffer, image,
5052 src_layout, dst_layout,
5053 src_queue_mask, dst_queue_mask,
5054 range);
5055 return;
5056 }
5057
5058 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5059 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5060 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5061 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5062 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5063 radv_decompress_dcc(cmd_buffer, image, range);
5064 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5065 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5066 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5067 }
5068 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5069 bool fce_eliminate = false, fmask_expand = false;
5070
5071 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5072 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5073 fce_eliminate = true;
5074 }
5075
5076 if (radv_image_has_fmask(image)) {
5077 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5078 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5079 /* A FMASK decompress is required before doing
5080 * a MSAA decompress using FMASK.
5081 */
5082 fmask_expand = true;
5083 }
5084 }
5085
5086 if (fce_eliminate || fmask_expand)
5087 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5088
5089 if (fmask_expand)
5090 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5091 }
5092 }
5093
5094 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5095 struct radv_image *image,
5096 VkImageLayout src_layout,
5097 VkImageLayout dst_layout,
5098 uint32_t src_family,
5099 uint32_t dst_family,
5100 const VkImageSubresourceRange *range,
5101 struct radv_sample_locations_state *sample_locs)
5102 {
5103 if (image->exclusive && src_family != dst_family) {
5104 /* This is an acquire or a release operation and there will be
5105 * a corresponding release/acquire. Do the transition in the
5106 * most flexible queue. */
5107
5108 assert(src_family == cmd_buffer->queue_family_index ||
5109 dst_family == cmd_buffer->queue_family_index);
5110
5111 if (src_family == VK_QUEUE_FAMILY_EXTERNAL)
5112 return;
5113
5114 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5115 return;
5116
5117 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5118 (src_family == RADV_QUEUE_GENERAL ||
5119 dst_family == RADV_QUEUE_GENERAL))
5120 return;
5121 }
5122
5123 if (src_layout == dst_layout)
5124 return;
5125
5126 unsigned src_queue_mask =
5127 radv_image_queue_family_mask(image, src_family,
5128 cmd_buffer->queue_family_index);
5129 unsigned dst_queue_mask =
5130 radv_image_queue_family_mask(image, dst_family,
5131 cmd_buffer->queue_family_index);
5132
5133 if (vk_format_is_depth(image->vk_format)) {
5134 radv_handle_depth_image_transition(cmd_buffer, image,
5135 src_layout, dst_layout,
5136 src_queue_mask, dst_queue_mask,
5137 range, sample_locs);
5138 } else {
5139 radv_handle_color_image_transition(cmd_buffer, image,
5140 src_layout, dst_layout,
5141 src_queue_mask, dst_queue_mask,
5142 range);
5143 }
5144 }
5145
5146 struct radv_barrier_info {
5147 uint32_t eventCount;
5148 const VkEvent *pEvents;
5149 VkPipelineStageFlags srcStageMask;
5150 VkPipelineStageFlags dstStageMask;
5151 };
5152
5153 static void
5154 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5155 uint32_t memoryBarrierCount,
5156 const VkMemoryBarrier *pMemoryBarriers,
5157 uint32_t bufferMemoryBarrierCount,
5158 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5159 uint32_t imageMemoryBarrierCount,
5160 const VkImageMemoryBarrier *pImageMemoryBarriers,
5161 const struct radv_barrier_info *info)
5162 {
5163 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5164 enum radv_cmd_flush_bits src_flush_bits = 0;
5165 enum radv_cmd_flush_bits dst_flush_bits = 0;
5166
5167 for (unsigned i = 0; i < info->eventCount; ++i) {
5168 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5169 uint64_t va = radv_buffer_get_va(event->bo);
5170
5171 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5172
5173 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5174
5175 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5176 assert(cmd_buffer->cs->cdw <= cdw_max);
5177 }
5178
5179 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5180 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5181 NULL);
5182 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5183 NULL);
5184 }
5185
5186 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5187 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5188 NULL);
5189 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5190 NULL);
5191 }
5192
5193 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5194 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5195
5196 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5197 image);
5198 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5199 image);
5200 }
5201
5202 /* The Vulkan spec 1.1.98 says:
5203 *
5204 * "An execution dependency with only
5205 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5206 * will only prevent that stage from executing in subsequently
5207 * submitted commands. As this stage does not perform any actual
5208 * execution, this is not observable - in effect, it does not delay
5209 * processing of subsequent commands. Similarly an execution dependency
5210 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5211 * will effectively not wait for any prior commands to complete."
5212 */
5213 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5214 radv_stage_flush(cmd_buffer, info->srcStageMask);
5215 cmd_buffer->state.flush_bits |= src_flush_bits;
5216
5217 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5218 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5219
5220 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5221 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5222 SAMPLE_LOCATIONS_INFO_EXT);
5223 struct radv_sample_locations_state sample_locations = {};
5224
5225 if (sample_locs_info) {
5226 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5227 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5228 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5229 sample_locations.count = sample_locs_info->sampleLocationsCount;
5230 typed_memcpy(&sample_locations.locations[0],
5231 sample_locs_info->pSampleLocations,
5232 sample_locs_info->sampleLocationsCount);
5233 }
5234
5235 radv_handle_image_transition(cmd_buffer, image,
5236 pImageMemoryBarriers[i].oldLayout,
5237 pImageMemoryBarriers[i].newLayout,
5238 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5239 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5240 &pImageMemoryBarriers[i].subresourceRange,
5241 sample_locs_info ? &sample_locations : NULL);
5242 }
5243
5244 /* Make sure CP DMA is idle because the driver might have performed a
5245 * DMA operation for copying or filling buffers/images.
5246 */
5247 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5248 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5249 si_cp_dma_wait_for_idle(cmd_buffer);
5250
5251 cmd_buffer->state.flush_bits |= dst_flush_bits;
5252 }
5253
5254 void radv_CmdPipelineBarrier(
5255 VkCommandBuffer commandBuffer,
5256 VkPipelineStageFlags srcStageMask,
5257 VkPipelineStageFlags destStageMask,
5258 VkBool32 byRegion,
5259 uint32_t memoryBarrierCount,
5260 const VkMemoryBarrier* pMemoryBarriers,
5261 uint32_t bufferMemoryBarrierCount,
5262 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5263 uint32_t imageMemoryBarrierCount,
5264 const VkImageMemoryBarrier* pImageMemoryBarriers)
5265 {
5266 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5267 struct radv_barrier_info info;
5268
5269 info.eventCount = 0;
5270 info.pEvents = NULL;
5271 info.srcStageMask = srcStageMask;
5272 info.dstStageMask = destStageMask;
5273
5274 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5275 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5276 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5277 }
5278
5279
5280 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5281 struct radv_event *event,
5282 VkPipelineStageFlags stageMask,
5283 unsigned value)
5284 {
5285 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5286 uint64_t va = radv_buffer_get_va(event->bo);
5287
5288 si_emit_cache_flush(cmd_buffer);
5289
5290 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5291
5292 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5293
5294 /* Flags that only require a top-of-pipe event. */
5295 VkPipelineStageFlags top_of_pipe_flags =
5296 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5297
5298 /* Flags that only require a post-index-fetch event. */
5299 VkPipelineStageFlags post_index_fetch_flags =
5300 top_of_pipe_flags |
5301 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5302 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5303
5304 /* Make sure CP DMA is idle because the driver might have performed a
5305 * DMA operation for copying or filling buffers/images.
5306 */
5307 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5308 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5309 si_cp_dma_wait_for_idle(cmd_buffer);
5310
5311 /* TODO: Emit EOS events for syncing PS/CS stages. */
5312
5313 if (!(stageMask & ~top_of_pipe_flags)) {
5314 /* Just need to sync the PFP engine. */
5315 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5316 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5317 S_370_WR_CONFIRM(1) |
5318 S_370_ENGINE_SEL(V_370_PFP));
5319 radeon_emit(cs, va);
5320 radeon_emit(cs, va >> 32);
5321 radeon_emit(cs, value);
5322 } else if (!(stageMask & ~post_index_fetch_flags)) {
5323 /* Sync ME because PFP reads index and indirect buffers. */
5324 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5325 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5326 S_370_WR_CONFIRM(1) |
5327 S_370_ENGINE_SEL(V_370_ME));
5328 radeon_emit(cs, va);
5329 radeon_emit(cs, va >> 32);
5330 radeon_emit(cs, value);
5331 } else {
5332 /* Otherwise, sync all prior GPU work using an EOP event. */
5333 si_cs_emit_write_event_eop(cs,
5334 cmd_buffer->device->physical_device->rad_info.chip_class,
5335 radv_cmd_buffer_uses_mec(cmd_buffer),
5336 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5337 EOP_DATA_SEL_VALUE_32BIT, va, value,
5338 cmd_buffer->gfx9_eop_bug_va);
5339 }
5340
5341 assert(cmd_buffer->cs->cdw <= cdw_max);
5342 }
5343
5344 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5345 VkEvent _event,
5346 VkPipelineStageFlags stageMask)
5347 {
5348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5349 RADV_FROM_HANDLE(radv_event, event, _event);
5350
5351 write_event(cmd_buffer, event, stageMask, 1);
5352 }
5353
5354 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5355 VkEvent _event,
5356 VkPipelineStageFlags stageMask)
5357 {
5358 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5359 RADV_FROM_HANDLE(radv_event, event, _event);
5360
5361 write_event(cmd_buffer, event, stageMask, 0);
5362 }
5363
5364 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5365 uint32_t eventCount,
5366 const VkEvent* pEvents,
5367 VkPipelineStageFlags srcStageMask,
5368 VkPipelineStageFlags dstStageMask,
5369 uint32_t memoryBarrierCount,
5370 const VkMemoryBarrier* pMemoryBarriers,
5371 uint32_t bufferMemoryBarrierCount,
5372 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5373 uint32_t imageMemoryBarrierCount,
5374 const VkImageMemoryBarrier* pImageMemoryBarriers)
5375 {
5376 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5377 struct radv_barrier_info info;
5378
5379 info.eventCount = eventCount;
5380 info.pEvents = pEvents;
5381 info.srcStageMask = 0;
5382
5383 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5384 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5385 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5386 }
5387
5388
5389 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5390 uint32_t deviceMask)
5391 {
5392 /* No-op */
5393 }
5394
5395 /* VK_EXT_conditional_rendering */
5396 void radv_CmdBeginConditionalRenderingEXT(
5397 VkCommandBuffer commandBuffer,
5398 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5399 {
5400 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5401 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5402 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5403 bool draw_visible = true;
5404 uint64_t pred_value = 0;
5405 uint64_t va, new_va;
5406 unsigned pred_offset;
5407
5408 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5409
5410 /* By default, if the 32-bit value at offset in buffer memory is zero,
5411 * then the rendering commands are discarded, otherwise they are
5412 * executed as normal. If the inverted flag is set, all commands are
5413 * discarded if the value is non zero.
5414 */
5415 if (pConditionalRenderingBegin->flags &
5416 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5417 draw_visible = false;
5418 }
5419
5420 si_emit_cache_flush(cmd_buffer);
5421
5422 /* From the Vulkan spec 1.1.107:
5423 *
5424 * "If the 32-bit value at offset in buffer memory is zero, then the
5425 * rendering commands are discarded, otherwise they are executed as
5426 * normal. If the value of the predicate in buffer memory changes while
5427 * conditional rendering is active, the rendering commands may be
5428 * discarded in an implementation-dependent way. Some implementations
5429 * may latch the value of the predicate upon beginning conditional
5430 * rendering while others may read it before every rendering command."
5431 *
5432 * But, the AMD hardware treats the predicate as a 64-bit value which
5433 * means we need a workaround in the driver. Luckily, it's not required
5434 * to support if the value changes when predication is active.
5435 *
5436 * The workaround is as follows:
5437 * 1) allocate a 64-value in the upload BO and initialize it to 0
5438 * 2) copy the 32-bit predicate value to the upload BO
5439 * 3) use the new allocated VA address for predication
5440 *
5441 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5442 * in ME (+ sync PFP) instead of PFP.
5443 */
5444 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5445
5446 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5447
5448 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5449 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5450 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5451 COPY_DATA_WR_CONFIRM);
5452 radeon_emit(cs, va);
5453 radeon_emit(cs, va >> 32);
5454 radeon_emit(cs, new_va);
5455 radeon_emit(cs, new_va >> 32);
5456
5457 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5458 radeon_emit(cs, 0);
5459
5460 /* Enable predication for this command buffer. */
5461 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5462 cmd_buffer->state.predicating = true;
5463
5464 /* Store conditional rendering user info. */
5465 cmd_buffer->state.predication_type = draw_visible;
5466 cmd_buffer->state.predication_va = new_va;
5467 }
5468
5469 void radv_CmdEndConditionalRenderingEXT(
5470 VkCommandBuffer commandBuffer)
5471 {
5472 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5473
5474 /* Disable predication for this command buffer. */
5475 si_emit_set_predication_state(cmd_buffer, false, 0);
5476 cmd_buffer->state.predicating = false;
5477
5478 /* Reset conditional rendering user info. */
5479 cmd_buffer->state.predication_type = -1;
5480 cmd_buffer->state.predication_va = 0;
5481 }
5482
5483 /* VK_EXT_transform_feedback */
5484 void radv_CmdBindTransformFeedbackBuffersEXT(
5485 VkCommandBuffer commandBuffer,
5486 uint32_t firstBinding,
5487 uint32_t bindingCount,
5488 const VkBuffer* pBuffers,
5489 const VkDeviceSize* pOffsets,
5490 const VkDeviceSize* pSizes)
5491 {
5492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5493 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5494 uint8_t enabled_mask = 0;
5495
5496 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5497 for (uint32_t i = 0; i < bindingCount; i++) {
5498 uint32_t idx = firstBinding + i;
5499
5500 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5501 sb[idx].offset = pOffsets[i];
5502 sb[idx].size = pSizes[i];
5503
5504 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5505 sb[idx].buffer->bo);
5506
5507 enabled_mask |= 1 << idx;
5508 }
5509
5510 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5511
5512 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5513 }
5514
5515 static void
5516 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5517 {
5518 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5519 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5520
5521 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5522 radeon_emit(cs,
5523 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5524 S_028B94_RAST_STREAM(0) |
5525 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5526 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5527 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5528 radeon_emit(cs, so->hw_enabled_mask &
5529 so->enabled_stream_buffers_mask);
5530
5531 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5532 }
5533
5534 static void
5535 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5536 {
5537 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5538 bool old_streamout_enabled = so->streamout_enabled;
5539 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5540
5541 so->streamout_enabled = enable;
5542
5543 so->hw_enabled_mask = so->enabled_mask |
5544 (so->enabled_mask << 4) |
5545 (so->enabled_mask << 8) |
5546 (so->enabled_mask << 12);
5547
5548 if ((old_streamout_enabled != so->streamout_enabled) ||
5549 (old_hw_enabled_mask != so->hw_enabled_mask))
5550 radv_emit_streamout_enable(cmd_buffer);
5551 }
5552
5553 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5554 {
5555 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5556 unsigned reg_strmout_cntl;
5557
5558 /* The register is at different places on different ASICs. */
5559 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5560 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5561 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5562 } else {
5563 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5564 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5565 }
5566
5567 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5568 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5569
5570 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5571 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5572 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5573 radeon_emit(cs, 0);
5574 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5575 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5576 radeon_emit(cs, 4); /* poll interval */
5577 }
5578
5579 void radv_CmdBeginTransformFeedbackEXT(
5580 VkCommandBuffer commandBuffer,
5581 uint32_t firstCounterBuffer,
5582 uint32_t counterBufferCount,
5583 const VkBuffer* pCounterBuffers,
5584 const VkDeviceSize* pCounterBufferOffsets)
5585 {
5586 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5587 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5588 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5589 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5590 uint32_t i;
5591
5592 radv_flush_vgt_streamout(cmd_buffer);
5593
5594 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5595 for_each_bit(i, so->enabled_mask) {
5596 int32_t counter_buffer_idx = i - firstCounterBuffer;
5597 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5598 counter_buffer_idx = -1;
5599
5600 /* AMD GCN binds streamout buffers as shader resources.
5601 * VGT only counts primitives and tells the shader through
5602 * SGPRs what to do.
5603 */
5604 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5605 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5606 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5607
5608 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5609
5610 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5611 /* The array of counter buffers is optional. */
5612 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5613 uint64_t va = radv_buffer_get_va(buffer->bo);
5614
5615 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5616
5617 /* Append */
5618 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5619 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5620 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5621 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5622 radeon_emit(cs, 0); /* unused */
5623 radeon_emit(cs, 0); /* unused */
5624 radeon_emit(cs, va); /* src address lo */
5625 radeon_emit(cs, va >> 32); /* src address hi */
5626
5627 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5628 } else {
5629 /* Start from the beginning. */
5630 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5631 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5632 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5633 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5634 radeon_emit(cs, 0); /* unused */
5635 radeon_emit(cs, 0); /* unused */
5636 radeon_emit(cs, 0); /* unused */
5637 radeon_emit(cs, 0); /* unused */
5638 }
5639 }
5640
5641 radv_set_streamout_enable(cmd_buffer, true);
5642 }
5643
5644 void radv_CmdEndTransformFeedbackEXT(
5645 VkCommandBuffer commandBuffer,
5646 uint32_t firstCounterBuffer,
5647 uint32_t counterBufferCount,
5648 const VkBuffer* pCounterBuffers,
5649 const VkDeviceSize* pCounterBufferOffsets)
5650 {
5651 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5652 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5653 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5654 uint32_t i;
5655
5656 radv_flush_vgt_streamout(cmd_buffer);
5657
5658 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5659 for_each_bit(i, so->enabled_mask) {
5660 int32_t counter_buffer_idx = i - firstCounterBuffer;
5661 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5662 counter_buffer_idx = -1;
5663
5664 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5665 /* The array of counters buffer is optional. */
5666 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5667 uint64_t va = radv_buffer_get_va(buffer->bo);
5668
5669 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5670
5671 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5672 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5673 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5674 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5675 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5676 radeon_emit(cs, va); /* dst address lo */
5677 radeon_emit(cs, va >> 32); /* dst address hi */
5678 radeon_emit(cs, 0); /* unused */
5679 radeon_emit(cs, 0); /* unused */
5680
5681 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5682 }
5683
5684 /* Deactivate transform feedback by zeroing the buffer size.
5685 * The counters (primitives generated, primitives emitted) may
5686 * be enabled even if there is not buffer bound. This ensures
5687 * that the primitives-emitted query won't increment.
5688 */
5689 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5690
5691 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5692 }
5693
5694 radv_set_streamout_enable(cmd_buffer, false);
5695 }
5696
5697 void radv_CmdDrawIndirectByteCountEXT(
5698 VkCommandBuffer commandBuffer,
5699 uint32_t instanceCount,
5700 uint32_t firstInstance,
5701 VkBuffer _counterBuffer,
5702 VkDeviceSize counterBufferOffset,
5703 uint32_t counterOffset,
5704 uint32_t vertexStride)
5705 {
5706 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5707 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5708 struct radv_draw_info info = {};
5709
5710 info.instance_count = instanceCount;
5711 info.first_instance = firstInstance;
5712 info.strmout_buffer = counterBuffer;
5713 info.strmout_buffer_offset = counterBufferOffset;
5714 info.stride = vertexStride;
5715
5716 radv_draw(cmd_buffer, &info);
5717 }
5718
5719 /* VK_AMD_buffer_marker */
5720 void radv_CmdWriteBufferMarkerAMD(
5721 VkCommandBuffer commandBuffer,
5722 VkPipelineStageFlagBits pipelineStage,
5723 VkBuffer dstBuffer,
5724 VkDeviceSize dstOffset,
5725 uint32_t marker)
5726 {
5727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5728 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5729 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5730 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5731
5732 si_emit_cache_flush(cmd_buffer);
5733
5734 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5735 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5736 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5737 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5738 COPY_DATA_WR_CONFIRM);
5739 radeon_emit(cs, marker);
5740 radeon_emit(cs, 0);
5741 radeon_emit(cs, va);
5742 radeon_emit(cs, va >> 32);
5743 } else {
5744 si_cs_emit_write_event_eop(cs,
5745 cmd_buffer->device->physical_device->rad_info.chip_class,
5746 radv_cmd_buffer_uses_mec(cmd_buffer),
5747 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5748 EOP_DATA_SEL_VALUE_32BIT,
5749 va, marker,
5750 cmd_buffer->gfx9_eop_bug_va);
5751 }
5752 }