refer to signals directly in Test Core

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 68c30790934cc4bd7018c4766396ce5da9c06295..c013ed2a88c6a288b8f21b0fa78cfb2d3ad64017 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -57,7 +57,7 @@ class NonProductionCore(Elaboratable):
         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
         pi = self.l0.l0.dports[0].pi
 
-        # Instruction memory
+        # Test Instruction memory
         self.imem = TestMemory(32, idepth)
 
         # function units (only one each)
@@ -75,6 +75,10 @@ class NonProductionCore(Elaboratable):
         self.issue_i = Signal(reset_less=True)
         self.busy_o = Signal(reset_less=True)
 
+        # instruction input
+        self.bigendian_i = self.pdecode2.dec.bigendian
+        self.raw_opcode_i = self.pdecode2.dec.raw_opcode_in
+
     def elaborate(self, platform):
         m = Module()
 

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index ccc7f7de76de36b4afd0e8105eec4f58bafe6a55..c2a0692e4162238790efbd78fd5c31bd43031709 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -68,7 +68,7 @@ class TestRunner(FHDLTestCase):
         pdecode2 = core.pdecode2
         l0 = core.l0
 
-        comb += pdecode2.dec.raw_opcode_in.eq(instruction)
+        comb += core.raw_opcode_i.eq(instruction)
         comb += core.ivalid_i.eq(ivalid_i)
 
         # temporary hack: says "go" immediately for both address gen and ST
@@ -137,7 +137,7 @@ class TestRunner(FHDLTestCase):
                     print(code)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield core.bigendian_i.eq(0)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield ivalid_i.eq(1)
                     yield Settle()