Correct incorrect output bit size

diff --git a/TLB/src/AddressEncoder.py b/TLB/src/AddressEncoder.py
index c6437fc8e92ca9601a0b2ff5bfd4ca3c4d4ed59f..53e2479e6655c5d33023b3c27076fc41e5840750 100644 (file)
--- a/TLB/src/AddressEncoder.py
+++ b/TLB/src/AddressEncoder.py
@@ -13,7 +13,7 @@ class AddressEncoder():
         # Output
         self.single_match = Signal(1)
         self.multiple_match = Signal(1)
-        self.o = Signal(width)
+        self.o = Signal(max=width)
         
     def elaborate(self, platform=None):
         m = Module()