get score6600_multi.py working again

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 23c60100c2fb41ac0bff3ef8f85cfe508d82d9c9..42f38cb4a1fc916b763394fdf3e4426babe011f9 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -281,6 +281,11 @@ class BranchOp(Elaboratable):
 
 class BranchALU(Elaboratable):
     def __init__(self, width):
+        self.p = Dummy() # make look like nmutil pipeline API
+        self.p.data_i = Dummy()
+        self.p.data_i.ctx = Dummy()
+        self.n = Dummy() # make look like nmutil pipeline API
+        self.n.data_o = Dummy()
         self.p.valid_i = Signal()
         self.p.ready_o = Signal()
         self.n.ready_i = Signal()

diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py
index 46398bd95c6833b3ecfff50580d716853de005e5..95f12dc37c2105b69a9d8b144d27664b62f0df37 100644 (file)
--- a/src/soc/experiment/score6600_multi.py
+++ b/src/soc/experiment/score6600_multi.py
@@ -4,7 +4,7 @@ from nmigen.hdl.ast import unsigned
 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory
 from nmigen.back.pysim import Delay
 
-from soc.regfile.regfile import RegFileArray, treereduce
+from soc.regfile.regfile import RegFileArray, ortreereduce
 from soc.scoremulti.fu_fu_matrix import FUFUDepMatrix
 from soc.scoremulti.fu_reg_matrix import FURegDepMatrix
 from soc.scoreboard.global_pending import GlobalPending
@@ -170,10 +170,10 @@ class CompUnitsBase(Elaboratable):
         # protected by a single go_wr.  multi-issue requires a bus
         # to be inserted here.
         if self.units:
-            data_o = treereduce(self.units, "data_o")
+            data_o = ortreereduce(self.units, "data_o")
             comb += self.data_o.eq(data_o)
             if self.ldstmode:
-                addr_o = treereduce(self.units, "addr_o")
+                addr_o = ortreereduce(self.units, "addr_o")
                 comb += self.addr_o.eq(addr_o)
 
         for i, alu in enumerate(self.units):

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index aef0a5541523cc12d704da9ecf83bde21425b118..6653fa458471d98069581b0e1f34b82027c4aac5 100644 (file)
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -84,8 +84,8 @@ class Register(Elaboratable):
     def ports(self):
         res = list(self)
 
-def ortreereduce(tree):
-    return treereduce(tree, operator.or_, lambda x: getattr(x, "data_o"))
+def ortreereduce(tree, attr="data_o"):
+    return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
 
 
 class RegFileArray(Elaboratable):