Updated configuration suited for experiment9/tsmc_c018.

* Typo in coriolis2/settings.py (extra 'e' in blackboxNames parameter).
* Disable blackboxes generation in TSMC, they are directly supplied by
  the FlexLib DK.
* Strip the Makefile from unusable targets in real mode.
* Update doDesign.py for the latest Coriolis (H-Tree).

diff --git a/experiments9/tsmc_c018/Makefile b/experiments9/tsmc_c018/Makefile
index a5ad72a4fc94d46a444d66706510d7f233591e26..da212e34d1c1a768384789297bd4ceabcd9a51c4 100755 (executable)
--- a/experiments9/tsmc_c018/Makefile
+++ b/experiments9/tsmc_c018/Makefile
@@ -1,27 +1,32 @@
 
+                USE_DEBUG = No
+             USE_VALGRIND = No
+
         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
                DESIGN_KIT = FlexLib018
-#              DESIGN_KIT = cmos45
             YOSYS_FLATTEN = No
          YOSYS_BLACKBOXES = pll \
-                           spblock_512w64b8w
-#            YOSYS_SET_TOP = Yes
+                            spblock_512w64b8w
+#           YOSYS_SET_TOP = Yes
                     CHIP  = chip
                     CORE  = ls180
             USE_CLOCKTREE = Yes
-                USE_DEBUG = No
                   RM_CHIP = Yes
                 VST_FLAGS = --vst-uniquify-uppercase
 
-                 #NETLISTS = $(shell cat cells.lst)
+                #NETLISTS = $(shell cat cells.lst)
                  NETLISTS = ls180 libresoc
-#            YOSYS_FLATTEN = $(shell cat flatten.lst)
+#           YOSYS_FLATTEN = $(shell cat flatten.lst)
 
  include ./mk/design-flow.mk
 
-chip_r.vst: ls180.vst
-       -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
+
+chip_cts_r.vst: ls180.vst
+       -$(call scl_cols,$(call c2env, $(VALGRIND_COMMAND) cgt -tV --script=doDesign))
+
+chip_cts_r.gds: chip_cts_r.vst
+       -@echo "[INFO] Overriden default GDS rule (for use with FlexLib)."
 
 chip_r.ap: chip_r.vst
 
@@ -30,25 +35,6 @@ pinmux:
        ln -f -s ../../../pinmux/src/parse.py coriolis2/pinparse.py
        ln -f -s coriolis2/ls180 ls180
 
-# comment out for now
 blif:      ls180.blif
 vst:       ls180.vst
-
-lvx:       lvx-chip_r
-druc:      druc-chip_r
-dreal:     dreal-chip_r
-flatph:     flatph-chip_r
-view:      cgt-chip_r
-
-layout:    chip_r.ap
-gds:       chip_r.gds
-gds_flat:  chip_r_flat.gds
-cif:      chip_r.cif
-
-
-view:      cgt-chip_r
-sim:       asimut-ls180_r
-
-
-
-
+gds:       chip_cts_r.gds

diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py
index 2a72d23035e6033c40147c1632670a9bd6eb60d9..3672a3262bd8b54ce95b48e78acbd9b96cd2671e 100644 (file)
--- a/experiments9/tsmc_c018/coriolis2/settings.py
+++ b/experiments9/tsmc_c018/coriolis2/settings.py
@@ -102,7 +102,7 @@ def createPLLBlackbox ():
     createBlackbox(name='PLL',
                    libname='pll',
                    cellName='pll',
-                   blackboxeNames = [ 'pll'
+                   blackboxNames = [ 'pll'
                                      ],
                    real_name='real_pll') # probably
 
@@ -112,7 +112,7 @@ def createSramBlackbox ():
                    libname='LibreSOCMem',
                    cellName='spblock_512w64b8w',
                    # go back to only one blackbox
-                   blackboxeNames = [ 'spblock_512w64b8w'
+                   blackboxNames = [ 'spblock_512w64b8w'
                                      ],
                    real_name='real_sram')
 
@@ -133,6 +133,6 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     env = af.getEnvironment()
     env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
 
-with overlay.UpdateSession():
-    createSramBlackbox()
-    # createPLLBlackbox ()
+#with overlay.UpdateSession():
+#    createSramBlackbox()
+#    createPLLBlackbox ()

diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py
index 7c9573259767fe484019661b821d87eb8f26a520..816b1de622631c79c3ad022edd64c3f6f6ad8348 100644 (file)
--- a/experiments9/tsmc_c018/doDesign.py
+++ b/experiments9/tsmc_c018/doDesign.py
@@ -23,6 +23,7 @@ from   plugins.alpha.block.configuration  import IoPin, GaugeConf
 from   plugins.alpha.core2chip.libresocio import CoreToChip
 from   plugins.alpha.chip.configuration   import ChipConf
 from   plugins.alpha.chip.chip            import Chip
+#from   plugins.alpha.utils                import rgetInstanceMatching
 
 
 af = CRL.AllianceFramework.get()
@@ -130,11 +131,11 @@ def scriptMain (**kw):
     """The mandatory function to be called by Coriolis CGT/Unicorn."""
     global af
    #helpers.setTraceLevel( 550 )
-   #Breakpoint.setStopLevel( 100 )
+   #Breakpoint.setStopLevel( 99 )
     rvalue     = True
     coreSizeX  = u(51*90.0)
     coreSizeY  = u(56*90.0)
-    chipBorder = u(2*214.0 + 10*13.0)
+    chipBorder = u(2*214.0 + 8*13.0)
     ioSpecs    = IoSpecs()
    #pinmuxFile = './non_generated/litex_pinpads.json'
    #pinmuxFile = './coriolis2/ls180/litex_pinpads.json'
@@ -147,9 +148,12 @@ def scriptMain (**kw):
     ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'sdram_dq_{}', 'sdram_dq({})', 'sdram_dq_i({})', 'sdram_dq_oe({})', 'sdram_dq_o({})'), range(0,16) )
     ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'sdram_ba_{}', 'sdram_ba({})', 'sdram_ba({})'), 2 )
     ioPadsSpec += doIoPowerCap( IoPin.EAST|IoPin.A_END )
+    ioPadsSpec += [ (IoPin.EAST             , None, 'sys_pll_testout_o', 'sys_pll_testout_o', 'sys_pll_testout_o' )
+                  , (IoPin.EAST|IoPin.ANALOG, None, 'sys_pll_vco_o'    , 'sys_pll_vco_o'    , 'sys_pll_vco_o' )
+                  ]
    # I/O pads, West side.
     ioPadsSpec += doIoPowerCap( IoPin.WEST|IoPin.A_BEGIN )
-    ioPadsSpec += doIoPinVector( (IoPin.WEST , None,   'nc_{}', '  nc({})',   'nc({})'), range(40) )
+    ioPadsSpec += doIoPinVector( (IoPin.WEST , None,   'nc_{}', '  nc({})',   'nc({})'), range(36) )
    #ioPadsSpec += doIoPinVector( (IoPin.WEST , None,  'pwm_{}',  'pwm({})',  'pwm({})'),  2 )
     ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'eint_{}',  'eint_{}',  'eint_{}'),  3 )
     ioPadsSpec += [ (IoPin.WEST , None, 'spimaster_clk' , 'spimaster_clk' , 'spimaster_clk' )
@@ -168,8 +172,6 @@ def scriptMain (**kw):
                   , (IoPin.NORTH, None, 'jtag_tdo'     , 'jtag_tdo'     , 'jtag_tdo' )
                   , (IoPin.NORTH, None, 'jtag_tck'     , 'jtag_tck'     , 'jtag_tck' )
                   , (IoPin.NORTH, None, 'sys_clk'      , 'sys_clk'      , 'sys_clk' )
-                  , (IoPin.NORTH, None, 'sys_pll_testout_o' , 'sys_pll_testout_o' , 'sys_pll_testout_o' )
-                  , (IoPin.NORTH, None, 'sys_pll_vco_o', 'sys_pll_vco_o', 'sys_pll_vco_o' )
                   ]
     ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'sys_clksel_i{}', 'sys_clksel_i({})', 'sys_clksel_i({})'), 2 )
     ioPadsSpec += doIoPowerCap( IoPin.NORTH|IoPin.A_END )
@@ -200,7 +202,7 @@ def scriptMain (**kw):
         if editor: editor.setCell( cell )
        #ls180Conf = ChipConf( cell, ioPads=ioSpecs.ioPadsSpec )
         ls180Conf = ChipConf( cell, ioPads=ioPadsSpec )
-        ls180Conf.cfg.etesian.bloat = 'nsxlib'
+        ls180Conf.cfg.etesian.bloat = 'Flexlib'
         ls180Conf.cfg.etesian.uniformDensity = True
         ls180Conf.cfg.etesian.aspectRatio = 1.0
         ls180Conf.cfg.etesian.spaceMargin = 0.05
@@ -225,17 +227,16 @@ def scriptMain (**kw):
         ls180Conf.chipConf.ioPadGauge = 'LibreSOCIO'
         ls180Conf.coreSize = (coreSizeX, coreSizeY)
         ls180Conf.chipSize = (coreSizeX + chipBorder + u(5.0), coreSizeY + chipBorder - u(0.04) )
+       #ls180Conf.useHTree( 'core.subckt_12941_test_issuer.ti_coresync_clk' )
+        ls180Conf.useHTree( 'core.por_clk' )
+        ls180Conf.useHTree( 'jtag_tck_from_pad' )
 
-        #`tiId & sramId are dependent on Yosys. They need to be adjusted whenever
-        # the design changes.
-        tiId   = 12969
-        sramId = 3482
-        tiPath = 'subckt_{}_test_issuer.subckt_1_ti.'.format(tiId)
+        tiPath = 'test_issuer.ti.'
         sramDatas \
-            = [ [tiPath+'subckt_{}_sram4k_0.subckt_152_spblock512w64b8w_0.real_sram'.format(sramId  ), -2]
-              , [tiPath+'subckt_{}_sram4k_1.subckt_152_spblock512w64b8w_1.real_sram'.format(sramId+1),  3]
-              , [tiPath+'subckt_{}_sram4k_2.subckt_152_spblock512w64b8w_2.real_sram'.format(sramId+2),  2]
-              , [tiPath+'subckt_{}_sram4k_3.subckt_152_spblock512w64b8w_3.real_sram'.format(sramId+3),  3]
+            = [ ['test_issuer.ti.sram4k_0.spblock_512w64b8w', -2]
+              , ['test_issuer.ti.sram4k_1.spblock_512w64b8w',  3]
+              , ['test_issuer.ti.sram4k_2.spblock_512w64b8w',  2]
+              , ['test_issuer.ti.sram4k_3.spblock_512w64b8w',  3]
               ]
 
         ls180ToChip = CoreToChip( ls180Conf )
@@ -259,15 +260,13 @@ def scriptMain (**kw):
                     )
                 if i+1 < len(sramDatas):
                     originX += sramAb.getWidth() + 2*sliceHeight + sramDatas[i+1][1]*sliceStep
-            twoGrid     = DbU.fromGrid( 2 )
-            pll         = DataBase.getDB().getCell( 'gds_PLL' )
-            pllAb       = pll.getAbutmentBox()
-            pllInstance = Instance.create( cell, 'GDS_PLL', pll )
-            position    = Transformation( onGrid( coreAb.getXMax() - pllAb.getWidth () -pllAb.getXMin() )
-                                        , onGrid( coreAb.getYMax() - pllAb.getHeight() -pllAb.getYMin() )
-                                        , Transformation.Orientation.ID )
-            pllInstance.setTransformation( position )
-            pllInstance.setPlacementStatus( Instance.PlacementStatus.FIXED )
+            pllTransf = Transformation( coreAb.getXMax() # -u(234.0)
+                                      , coreAb.getYMax() - u(208.0)
+                                      , Transformation.Orientation.MX )
+            print( 'pllTransf={}'.format(pllTransf) )
+            chipBuilder.placeMacro( 'test_issuer.wrappll.pll' , pllTransf )
+        sys.stderr.flush()
+        sys.stdout.flush()
         Breakpoint.stop( 99, 'After core placement.' )
 
         rvalue = chipBuilder.doPnR()