remove use of reg3 in logical pipeline: CSV files moved RS to position 1

diff --git a/libreriscv b/libreriscv
index ce306badc535e08b5fc5e061b26290dce44166ff..177088bdebe14a2e1173f8302127bbde504c3116 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit ce306badc535e08b5fc5e061b26290dce44166ff
+Subproject commit 177088bdebe14a2e1173f8302127bbde504c3116

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 04778c6381e827dbe95d0a8b19dafacecb550e4b..c8f1ebc278002e348cd23782886b19799f61e530 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -29,13 +29,8 @@ def set_alu_inputs(alu, dec2, sim):
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
     # and place it into data_i.b
 
-    reg3_ok = yield dec2.e.read_reg3.ok
     reg1_ok = yield dec2.e.read_reg1.ok
-    assert reg3_ok != reg1_ok
-    if reg3_ok:
-        data1 = yield dec2.e.read_reg3.data
-        data1 = sim.gpr(data1).value
-    elif reg1_ok:
+    if reg1_ok:
         data1 = yield dec2.e.read_reg1.data
         data1 = sim.gpr(data1).value
     else: