should have been using common version of wb_get, not 8 duplicates

diff --git a/src/soc/experiment/test/test_compldst_multi_mmu.py b/src/soc/experiment/test/test_compldst_multi_mmu.py
index cb8bff00ea12f57b53bb39221724986be646a6e9..f3a3421bcbe76a1a018fe313612b3a9a5f04932f 100644 (file)
--- a/src/soc/experiment/test/test_compldst_multi_mmu.py
+++ b/src/soc/experiment/test/test_compldst_multi_mmu.py
@@ -27,7 +27,9 @@ from nmutil.util import Display
 
 from soc.config.loadstore import ConfigMemoryPortInterface
 from soc.experiment.test import pagetables
-from soc.experiment.test.test_wishbone import wb_get
+from openpower.test.wb_get import wb_get
+from openpower.test import wb_get as wbget
+
 
 ########################################
 
@@ -143,7 +145,7 @@ def ldst_sim(dut):
     assert(ld_data==data)
     print("dzbz test passed")
 
-    dut.stop = True # stop simulation
+    wbget.stop = True # stop simulation
 
 ########################################
 class TestLDSTCompUnitMMU(LDSTCompUnit):
@@ -194,10 +196,10 @@ def test_scoreboard_mmu():
     sim.add_clock(1e-6)
 
     dut.mem = pagetables.test1
-    dut.stop = False
+    wbget.stop = False
 
     sim.add_sync_process(wrap(ldst_sim(dut)))
-    sim.add_sync_process(wrap(wb_get(dut)))
+    sim.add_sync_process(wrap(wb_get(dut.cmpi.wb_bus(), dut.mem)))
     with sim.write_vcd('test_scoreboard_mmu.vcd'):
         sim.run()
 
@@ -252,10 +254,10 @@ def test_scoreboard_regspec_mmu():
     sim.add_clock(1e-6)
 
     dut.mem = pagetables.test1
-    dut.stop = False
+    wbget.stop = False
 
     sim.add_sync_process(wrap(ldst_sim(dut)))
-    sim.add_sync_process(wrap(wb_get(dut)))
+    sim.add_sync_process(wrap(wb_get(dut.cmpi.wb_bus(), dut.mem)))
     with sim.write_vcd('test_scoreboard_regspec_mmu.vcd'):
         sim.run()
 

diff --git a/src/soc/experiment/test/test_wishbone.py b/src/soc/experiment/test/test_wishbone.py
index fd3279ded07992875ccf996937b3d92e216b7164..d1a99381df83e7ee3534e6852fd7466b0c0e74fd 100644 (file)
--- a/src/soc/experiment/test/test_wishbone.py
+++ b/src/soc/experiment/test/test_wishbone.py
@@ -1,44 +1,2 @@
-def wb_get(dut):
-    """simulator process for getting memory load requests
-    """
-    mem = dut.mem
-    wb = dut.cmpi.wb_bus()
+from openpower.test.wb_get import wb_get
 
-    while not dut.stop:
-        while True: # wait for dc_valid
-            if dut.stop:
-                return
-            cyc = yield (wb.cyc)
-            stb = yield (wb.stb)
-            if cyc and stb:
-                break
-            yield
-        addr = (yield wb.adr) << 3
-        if addr not in mem:
-            print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
-
-        # read or write?
-        we = (yield wb.we)
-        if we:
-            store = (yield wb.dat_w)
-            sel = (yield wb.sel)
-            data = mem.get(addr, 0)
-            # note we assume 8-bit sel, here
-            res = 0
-            for i in range(8):
-                mask = 0xff << (i*8)
-                if sel & (1<<i):
-                    res |= store & mask
-                else:
-                    res |= data & mask
-            mem[addr] = res
-            print ("    DCACHE set %x mask %x data %x" % (addr, sel, res))
-        else:
-            data = mem.get(addr, 0)
-            yield wb.dat_r.eq(data)
-            print ("    DCACHE get %x data %x" % (addr, data))
-
-        yield wb.ack.eq(1)
-        yield
-        yield wb.ack.eq(0)
-        yield