somehow managed to miss out setting r1.forward_valid1 in dcache

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index f63ed5217dabec3edd86d4160e761491dd950f39..3bfe772fa95788127875553ea2b78f5a0448336a 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1529,6 +1529,7 @@ class DCache(Elaboratable):
                     sync += r1.wb.adr[:LINE_OFF_BITS-ROW_OFF_BITS].eq(row+1)
 
                 # Incoming acks processing
+                sync += r1.forward_valid1.eq(bus.ack)
                 with m.If(bus.ack):
                     srow = Signal(ROW_LINE_BITS)
                     comb += srow.eq(r1.store_row)