found an error in PartitionedAssign and PartitionedRepl

where Slice was accidentally being done on SimdSignal rather than
SimdSignals internal sig.  whilst this was a legitimate oversight
the bug should have been found when a NotImplemented SimdSignal.__Slice__
was added.

Project Development Practices were violated here by unit tests not
having been run, which would have easily detected the bug

diff --git a/src/ieee754/part_ass/assign.py b/src/ieee754/part_ass/assign.py
index 2a79cbbc596b65ea893b02cbeb79127811326bc5..81873bcbe7714f0167708832596f06110a04a29b 100644 (file)
--- a/src/ieee754/part_ass/assign.py
+++ b/src/ieee754/part_ass/assign.py
@@ -71,7 +71,8 @@ class PartitionedAssign(Elaboratable):
         start = keys[upto]
         end = keys[upto+numparts]
         print ("start end", start, end, len(x))
-        return x[start:end]
+        # access the underlying signal of SimdSignal directly
+        return x.sig[start:end]
 
     def elaborate(self, platform):
         m = Module()

diff --git a/src/ieee754/part_repl/repl.py b/src/ieee754/part_repl/repl.py
index 7347648370dc346a1e80ad642be82bdb3b19a401..05db372a5203dba1f4c5fe46af8d75ed802a2286 100644 (file)
--- a/src/ieee754/part_repl/repl.py
+++ b/src/ieee754/part_repl/repl.py
@@ -73,7 +73,8 @@ class PartitionedRepl(Elaboratable):
         start = keys[upto]
         end = keys[upto+numparts]
         print ("start end", start, end, len(x))
-        return x[start:end]
+        # access the underlying Signal of SimdSignal directly
+        return x.sig[start:end]
 
     def elaborate(self, platform):
         m = Module()