assert self.nclkouts < self.nclkouts_max
self.clkouts[self.nclkouts] = (cd, freq, phase, margin)
#create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
+ print("clock domain", cd.domain, freq, margin, self.nclkouts)
self.nclkouts += 1
def compute_config(self):
config["vco"] = vco_freq
config["clkfb_div"] = clkfb_div
#compute_config_log(self.logger, config)
+ print ("PLL config", config)
return config
raise ValueError("No PLL config found")
self.params["o_CLKO{}".format(n_to_l[n])] = clk
m = Module()
+ print ("params", self.params)
pll = Instance("EHXPLLL", **self.params)
m.submodules.pll = pll
return m
]
# Power-on delay (655us)
- podcnt = Signal(16, reset=2**16-1)
+ podcnt = Signal(3, reset=-1)
pod_done = Signal()
with m.If(podcnt != 0):
m.d.rawclk += podcnt.eq(podcnt-1)
cd_init = ClockDomain("init", local=False)
cd_sync = ClockDomain("sync", local=False)
cd_dramsync = ClockDomain("dramsync", local=False)
- m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=reset)
+ m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
pll.set_clkin_freq(100e6)
pll.create_clkout(ClockSignal("sync2x_unbuf"), 2*self.sys_clk_freq)
pll.create_clkout(ClockSignal("init"), 25e6)