# instruction go/monitor
self.go_insn_i = Signal(reset_less=True)
self.pc_o = Signal(64, reset_less=True)
- self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me"
- self.busy_o = core.busy_o
+ self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
+ self.core_start_i = Signal()
+ self.core_bigendian_i = Signal()
+ self.busy_o = Signal(reset_less=True)
+ self.halted_o = Signal(reset_less=True)
self.memerr_o = Signal(reset_less=True)
# FAST regfile read /write ports for PC and MSR
m.submodules.core = core = self.core
m.submodules.imem = imem = self.imem
+ # busy/halted signals from core
+ comb += self.busy_o.eq(core.busy_o)
+ comb += self.halted_o.eq(core.core_terminated_o)
+ comb += self.core_start_i.eq(core.core_start_i)
+ comb += self.core_bigendian_i.eq(core.bigendian_i)
+
# temporary hack: says "go" immediately for both address gen and ST
l0 = core.l0
ldst = core.fus.fus['ldst0']
for test in self.test_data:
# get core going
- yield core.bigendian_i.eq(bigendian)
- yield core.core_start_i.eq(1)
+ yield issuer.core_bigendian_i.eq(bigendian)
+ yield issuer.core_start_i.eq(1)
yield
- yield core.core_start_i.eq(0)
+ yield issuer.core_start_i.eq(0)
yield Settle()
print(test.name)
yield from wait_for_busy_hi(core)
yield from wait_for_busy_clear(core)
- terminated = yield core.core_terminated_o
+ terminated = yield issuer.halted_o
print ("terminated", terminated)
print ("sim", code)
# Memory check
yield from check_sim_memory(self, l0, sim, code)
- terminated = yield core.core_terminated_o
+ terminated = yield issuer.halted_o
if terminated:
break