start adding myhdl IO class

diff --git a/src/ifacebase.py b/src/ifacebase.py
index c5487a1c3946562e55902f3714ab5200b7b60cb9..72dbcc9d06ef579673275866d46f429dcc850993 100644 (file)
--- a/src/ifacebase.py
+++ b/src/ifacebase.py
@@ -66,7 +66,8 @@ class InterfacesBase(UserDict):
                 ln = ln.strip()
                 ln = ln.split("\t")
                 name = ln[0]
-                d = {'name': name}  # here we start to make the dictionary
+                d = {'name': name,  # here we start to make the dictionary
+                     'type': ln[1]}
                 if ln[1] == 'out':
                     d['action'] = True  # adding element to the dict
                 elif ln[1] == 'inout':

diff --git a/src/myhdl/pinmux_generator.py b/src/myhdl/pinmux_generator.py
index a9dab0106acc2a2efdb10fcc39a595a36716d1a8..733694ba20c9a2b33a093189357f06f7c4489bfe 100644 (file)
--- a/src/myhdl/pinmux_generator.py
+++ b/src/myhdl/pinmux_generator.py
@@ -1,4 +1,5 @@
 from parse import Parse
+from myhdl.pins import IO
 from ifacebase import InterfacesBase
 try:
     from string import maketrans
@@ -66,21 +67,9 @@ class Interface(object):
         self.single = single
         for p in pinspecs:
             _p = {}
-            _p.update(p)
-            if p.get('outen') is True:  # special case, generate 3 pins
-                del _p['outen']
-                for psuffix in ['out', 'outen', 'in']:
-                    # changing the name (like sda) to (twi_sda_out)
-                    _p['name'] = "%s_%s" % (self.pname(p['name']), psuffix)
-                    _p['action'] = psuffix != 'in'
-                    self.pins.append(Pin(**_p))
-                    # will look like {'name': 'twi_sda_out', 'action': True}
-                    # {'name': 'twi_sda_outen', 'action': True}
-                    #{'name': 'twi_sda_in', 'action': False}
-                    # NOTice - outen key is removed
-            else:
-                _p['name'] = self.pname(p['name'])
-                self.pins.append(Pin(**_p))
+            _p['name'] = self.pname(p['name'])
+            _p['typ'] = self.pname(p['type'])
+            self.pins.append(IO(**_p))
 
     def getifacetype(self, name):
         for p in self.pinspecs:
@@ -128,6 +117,6 @@ def init(p, ifaces):
 
 def pinmuxgen(pth=None, verify=True):
     p = Parse(pth, verify)
-    print p, dir(p)
+    print (p, dir(p))
     ifaces = Interfaces(pth)
     init(p, ifaces)

diff --git a/src/spec/testing.py b/src/spec/testing.py
index 27a5b26a5bd77ba969df71c8f177f86fb5f256bb..14055af4e59ee4b75857acf6fa37071cbec5fde8 100644 (file)
--- a/src/spec/testing.py
+++ b/src/spec/testing.py
@@ -1,4 +1,7 @@
-from UserDict import UserDict
+try:
+    from UserDict import UserDict
+except ImportError:
+    from collections import UserDict
 
 
 class Wire(object):
@@ -27,9 +30,9 @@ class Wires(UserDict):
 
 
 def dummytest(ps, output_dir, output_type):
-    print ps, output_dir, output_type
-    print dir(ps)
-    print ps.fnspec
+    print (ps, output_dir, output_type)
+    print (dir(ps))
+    print (ps.fnspec)
 
     # basically we need to replicate the entirety of the
     # verilog module's inputs and outputs, so that we can