--- /dev/null
+# IEEE Floating Point Adder (Single Precision)
+# Copyright (C) Jonathan P Dawson 2013
+# 2013-12-12
+
+from nmigen import Module
+from nmigen.cli import main, verilog
+
+from nmutil.singlepipe import ControlBase
+from nmutil.concurrentunit import ReservationStations, num_bits
+
+from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.pack import FPPackData
+from ieee754.fpcommon.normtopack import FPNormToPack
+from .specialcases import FPDivSpecialCasesDeNorm
+from .mulstages import FPDivStages
+
+
+
+class FPDIVBasePipe(ControlBase):
+ def __init__(self, width, id_wid):
+ ControlBase.__init__(self)
+ self.pipe1 = FPDivSpecialCasesDeNorm(width, id_wid)
+ self.pipe2 = FPDivStages(width, id_wid)
+ self.pipe3 = FPNormToPack(width, id_wid)
+
+ self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
+
+ def elaborate(self, platform):
+ m = ControlBase.elaborate(self, platform)
+ m.submodules.scnorm = self.pipe1
+ m.submodules.mulstages = self.pipe2
+ m.submodules.normpack = self.pipe3
+ m.d.comb += self._eqs
+ return m
+
+
+class FPDIVMuxInOut(ReservationStations):
+ """ Reservation-Station version of FPDIV pipeline.
+
+ * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+ * 2-stage multiplier pipeline
+ * fan-out on outputs (an array of FPPackData: z,mid)
+
+ Fan-in and Fan-out are combinatorial.
+ """
+ def __init__(self, width, num_rows):
+ self.width = width
+ self.id_wid = num_bits(width)
+ self.alu = FPDIVBasePipe(width, self.id_wid)
+ ReservationStations.__init__(self, num_rows)
+
+ def i_specfn(self):
+ return FPADDBaseData(self.width, self.id_wid)
+
+ def o_specfn(self):
+ return FPPackData(self.width, self.id_wid)