use sub-test in logical test_pipe_caller

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 298f359c9b61fad4789a0f6c1a388971b9642ab9..8af95ead98932cc8533de53010fc38b9a66984e1 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -158,6 +158,50 @@ class TestRunner(FHDLTestCase):
         super().__init__("run_all")
         self.test_data = test_data
 
+    def execute(self, alu,instruction, pdecode2, test):
+        print(test.name)
+        program = test.program
+        self.subTest(test.name)
+        simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                        test.mem, test.msr,
+                        bigendian=bigendian)
+        gen = program.generate_instructions()
+        instructions = list(zip(gen, program.assembly.splitlines()))
+
+        index = simulator.pc.CIA.value//4
+        while index < len(instructions):
+            ins, code = instructions[index]
+
+            print("0x{:X}".format(ins & 0xffffffff))
+            print(code)
+
+            # ask the decoder to decode this binary data (endian'd)
+            yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
+            yield instruction.eq(ins)          # raw binary instr.
+            yield Settle()
+            fn_unit = yield pdecode2.e.do.fn_unit
+            self.assertEqual(fn_unit, Function.LOGICAL.value, code)
+            yield from set_alu_inputs(alu, pdecode2, simulator)
+
+            # set valid for one cycle, propagate through pipeline...
+            yield alu.p.valid_i.eq(1)
+            yield
+            yield alu.p.valid_i.eq(0)
+
+            opname = code.split(' ')[0]
+            yield from simulator.call(opname)
+            index = simulator.pc.CIA.value//4
+
+            vld = yield alu.n.valid_o
+            while not vld:
+                yield
+                vld = yield alu.n.valid_o
+            yield
+
+            yield from self.check_alu_outputs(alu, pdecode2,
+                                              simulator, code)
+            yield Settle()
+
     def run_all(self):
         m = Module()
         comb = m.d.comb
@@ -181,47 +225,8 @@ class TestRunner(FHDLTestCase):
             for test in self.test_data:
                 print(test.name)
                 program = test.program
-                self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr,
-                                bigendian=bigendian)
-                gen = program.generate_instructions()
-                instructions = list(zip(gen, program.assembly.splitlines()))
-
-                index = simulator.pc.CIA.value//4
-                while index < len(instructions):
-                    ins, code = instructions[index]
-
-                    print("0x{:X}".format(ins & 0xffffffff))
-                    print(code)
-
-                    # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
-                    yield instruction.eq(ins)          # raw binary instr.
-                    yield Settle()
-                    fn_unit = yield pdecode2.e.do.fn_unit
-                    self.assertEqual(fn_unit, Function.LOGICAL.value, code)
-                    yield from set_alu_inputs(alu, pdecode2, simulator)
-
-                    # set valid for one cycle, propagate through pipeline...
-                    yield alu.p.valid_i.eq(1)
-                    yield
-                    yield alu.p.valid_i.eq(0)
-
-                    opname = code.split(' ')[0]
-                    yield from simulator.call(opname)
-                    index = simulator.pc.CIA.value//4
-
-                    vld = yield alu.n.valid_o
-                    while not vld:
-                        yield
-                        vld = yield alu.n.valid_o
-                    yield
-
-                    yield from self.check_alu_outputs(alu, pdecode2,
-                                                      simulator, code)
-                    yield Settle()
-
+                with self.subTest(test.name):
+                    yield from self.execute(alu, instruction, pdecode2, test)
 
         sim.add_sync_process(process)
         with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",