RS moved to port 1 (from port 3), remove need in ALU to read/mux into A operand

diff --git a/libreriscv b/libreriscv
index 177088bdebe14a2e1173f8302127bbde504c3116..6a79599c792e9271203c29082ee512a46930be85 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 177088bdebe14a2e1173f8302127bbde504c3116
+Subproject commit 6a79599c792e9271203c29082ee512a46930be85

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 56a8770a8ef500a4a997903aadfc1ed71189206c..8517dc741312b8fbd0c7f588ae17423f5b4af7e0 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -29,13 +29,8 @@ def set_alu_inputs(alu, dec2, sim):
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
     # and place it into data_i.b
 
-    reg3_ok = yield dec2.e.read_reg3.ok
     reg1_ok = yield dec2.e.read_reg1.ok
-    assert reg3_ok != reg1_ok
-    if reg3_ok:
-        data1 = yield dec2.e.read_reg3.data
-        data1 = sim.gpr(data1).value
-    elif reg1_ok:
+    if reg1_ok:
         data1 = yield dec2.e.read_reg1.data
         data1 = sim.gpr(data1).value
     else:

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 840bda32b59dabc8f5c151fd871bf5c54277ec42..0c7b0623b4b02ea742627f7ce950a3751260f95c 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -20,13 +20,8 @@ class ALUTestRunner(TestRunner):
         res = {}
 
         # RA (or RC)
-        reg3_ok = yield dec2.e.read_reg3.ok
         reg1_ok = yield dec2.e.read_reg1.ok
-        assert reg3_ok != reg1_ok
-        if reg3_ok:
-            data1 = yield dec2.e.read_reg3.data
-            res['a'] = sim.gpr(data1).value
-        elif reg1_ok:
+        if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
             res['a'] = sim.gpr(data1).value
 

diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py
index 1c9258b8e56e8f7d4c0500bb1709075c8945b856..0ba7e8d926b612ca1ca64b3eea72a1385864c1bf 100644 (file)
--- a/src/soc/fu/compunits/test/test_logical_compunit.py
+++ b/src/soc/fu/compunits/test/test_logical_compunit.py
@@ -20,13 +20,8 @@ class LogicalTestRunner(TestRunner):
         res = {}
 
         # RA (or RC)
-        reg3_ok = yield dec2.e.read_reg3.ok
         reg1_ok = yield dec2.e.read_reg1.ok
-        assert reg3_ok != reg1_ok
-        if reg3_ok:
-            data1 = yield dec2.e.read_reg3.data
-            res['a'] = sim.gpr(data1).value
-        elif reg1_ok:
+        if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
             res['a'] = sim.gpr(data1).value