static unsigned
bi_pack_add_select(bi_instruction *ins, bi_registers *regs)
{
- unsigned size = nir_alu_type_get_type_size(ins->src_types[0]);
+ ASSERTED unsigned size = nir_alu_type_get_type_size(ins->src_types[0]);
assert(size == 16);
unsigned swiz = (ins->swizzle[0][0] | (ins->swizzle[1][0] << 1));
bi_pack_add_cmp(bi_instruction *ins, bi_registers *regs)
{
nir_alu_type Tl = ins->src_types[0];
- nir_alu_type Tr = ins->src_types[1];
+ ASSERTED nir_alu_type Tr = ins->src_types[1];
nir_alu_type Bl = nir_alu_type_get_base_type(Tl);
if (Bl == nir_type_uint || Bl == nir_type_int) {
{
/* After these two, are we done? Determines tag */
bool done = clause->constant_count <= (index + 2);
- bool only = clause->constant_count <= (index + 1);
+ ASSERTED bool only = clause->constant_count <= (index + 1);
/* Is the constant we're packing for a branch? */
bool branches = clause->branch_constant && done;
fprintf(fp, "%s", bi_round_mode_name(ins->roundmode));
fprintf(fp, " ");
- bool succ = bi_print_dest_index(fp, ins, ins->dest);
+ ASSERTED bool succ = bi_print_dest_index(fp, ins, ins->dest);
assert(succ);
if (ins->dest_offset)
/* Check for scheduling restrictions */
bool can_fma = props & BI_SCHED_FMA;
- bool can_add = props & BI_SCHED_ADD;
+ ASSERTED bool can_add = props & BI_SCHED_ADD;
can_fma &= !bi_ambiguous_abs(ins);
can_fma &= !bi_icmp(ins);
imm = consts[5];
break;
default:
- assert(0);
- break;
+ unreachable("bad imm");
}
return imm | low_bits;
}
static inline uint32_t
__gen_sint(int32_t v, uint32_t start, uint32_t end)
{
- const int width = end - start + 1;
-
#ifndef NDEBUG
+ const int width = end - start + 1;
if (width < 64) {
const int64_t max = (1ll << (width - 1)) - 1;
const int64_t min = -(1ll << (width - 1));
/* Should we swap arguments? */
bool flip_src12 = false;
- unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
- unsigned dst_bitsize = nir_dest_bit_size(*dest);
+ ASSERTED unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
+ ASSERTED unsigned dst_bitsize = nir_dest_bit_size(*dest);
enum midgard_roundmode roundmode = MIDGARD_RTE;
else if (combined)
rt = MIDGARD_ZS_RT;
else
- assert(0);
+ unreachable("bad rt");
unsigned reg_z = ~0, reg_s = ~0;
if (combined) {
for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
unsigned v = swizzle[c];
- bool t_upper = v > 3;
+ ASSERTED bool t_upper = v > 3;
/* Ensure we're doing something sane */
for (unsigned i = 0; i < 4; ++i) {
/* Make sure we're duplicated */
bool u = (ins->mask & (1 << (2*i + 0))) != 0;
- bool v = (ins->mask & (1 << (2*i + 1))) != 0;
+ ASSERTED bool v = (ins->mask & (1 << (2*i + 1))) != 0;
assert(u == v);
packed |= (u << i);
/* Special register classes impose special constraints on who can read their
* values, so check that */
-static bool
+static bool ASSERTED
check_read_class(unsigned *classes, unsigned tag, unsigned node)
{
/* Non-nodes are implicitly ok */
}
}
-static bool
+static bool ASSERTED
check_write_class(unsigned *classes, unsigned tag, unsigned node)
{
/* Non-nodes are implicitly ok */