bitspec if now of type "Bit#(?)" or GenericIOType

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 4635d772ddc4d48eec4de665f641afe182ff0b6c..1a9b86b4ea64f09fa53a97b3a379809fbf245378 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -91,7 +91,7 @@ def pinmuxgen(pth=None, verify=True):
       // where each IO will have the same number of muxes.''')
 
         for cell in p.muxed_cells:
-            cnum = int(math.log(len(cell) - 1, 2))
+            cnum = 'Bit#(' + str(int(math.log(len(cell) - 1, 2))) + ')'
             bsv_file.write(mux_interface.ifacefmt(cell[0], cnum))
 
         bsv_file.write('''
@@ -128,7 +128,7 @@ def pinmuxgen(pth=None, verify=True):
 ''')
         for cell in p.muxed_cells:
             bsv_file.write(mux_interface.wirefmt(
-                cell[0], int(math.log(len(cell) - 1, 2))))
+                cell[0], 'Bit#('+str(int(math.log(len(cell) - 1, 2)))+')'))
 
         ifaces.wirefmt(bsv_file)
 
@@ -150,9 +150,9 @@ def pinmuxgen(pth=None, verify=True):
         for cell in p.muxed_cells:
             bsv_file.write(
                 mux_interface.ifacedef(
-                    cell[0], int(
+                    cell[0], 'Bit#(' + str(int(
                         math.log(
-                            len(cell) - 1, 2))))
+                            len(cell) - 1, 2))) + ')'))
         bsv_file.write('''
     endinterface;
     interface peripheral_side = interface PeripheralSide

diff --git a/src/bsv/wire_def.py b/src/bsv/wire_def.py
index 5b85f7f180371b9798547c7f314b69962c20b779..59431a2a41a816d5b433b27f21f3c04fb1c7787b 100644 (file)
--- a/src/bsv/wire_def.py
+++ b/src/bsv/wire_def.py
@@ -1,6 +1,6 @@
 # == Intermediate wire definitions, special cases ==#
 muxwire = '''
-      Wire#(Bit#({1})) wrcell{0}_mux<-mkDWire(0);'''
+      Wire#({1}) wrcell{0}_mux<-mkDWire(0);'''
 generic_io = '''
       GenericIOType cell{0}_mux_out=unpack(0);
       Wire#(Bit#(1)) cell{0}_mux_in<-mkDWire(0);