add "done" signal to CompALU and LDSTCompALU to be able to select between the

two types consistently

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index 7da6b5cf9fa06b9bfa766f769ac19f4f49caf90b..f7b5e411a739e770777ceb71d7bd09fe4e70e8c0 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -65,6 +65,7 @@ class ComputationUnitNoDelay(Elaboratable):
         self.data_o = Signal(rwid, reset_less=True) # Dest out
         self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request
         self.req_rel_o = Signal(reset_less=True) # release request out (valid_o)
+        self.done_o = self.req_rel_o # 'normalise' API
 
     def elaborate(self, platform):
         m = Module()

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index 50137c32140836782804bf91ea90d6040e78eb35..206f44876b00b6c1d94716e624a03e81208120d4 100644 (file)
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -117,6 +117,7 @@ class LDSTCompUnit(Elaboratable):
         self.adr_rel_o = Signal(reset_less=True) # request address (from mem)
         self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
         self.req_rel_o = Signal(reset_less=True) # request write (result)
+        self.done_o = Signal(reset_less=True) # final release signal
         self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
         self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST)
 
@@ -258,6 +259,10 @@ class LDSTCompUnit(Elaboratable):
             with m.If(self.req_rel_o):
                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 
+        # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
+        comb += self.done_o.eq((self.req_rel_o & ~op_ldst) |
+                               (self.adr_rel_o & op_ldst))
+
         # put the register directly onto the output bus on a go_write
         # this is "ALU mode".  go_wr_i *must* be deasserted on next clock
         with m.If(self.go_wr_i):
@@ -387,8 +392,6 @@ def add(dut, src1, src2, imm, imm_mode = False):
     return data
 
 def scoreboard_sim(dut):
-    data = yield from load(dut, 4, 0, 2)
-    return
     # two STs (different addresses)
     yield from store(dut, 4, 3, 2)
     yield from store(dut, 2, 9, 2)

diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py
index cc85ac500bc61963e8ce4207b56a0ce77d4aff4c..babce2439233f84c262c08795b873a6167197ec9 100644 (file)
--- a/src/soc/experiment/score6600.py
+++ b/src/soc/experiment/score6600.py
@@ -98,12 +98,12 @@ class CompUnitsBase(Elaboratable):
         self.busy_o = Signal(n_units, reset_less=True)
         self.rd_rel_o = Signal(n_units, reset_less=True)
         self.req_rel_o = Signal(n_units, reset_less=True)
+        self.done_o = Signal(n_units, reset_less=True)
         if ldstmode:
             self.ld_o = Signal(n_units, reset_less=True) # op is LD
             self.st_o = Signal(n_units, reset_less=True) # op is ST
             self.adr_rel_o = Signal(n_units, reset_less=True)
             self.sto_rel_o = Signal(n_units, reset_less=True)
-            self.req_rel_o = Signal(n_units, reset_less=True)
             self.load_mem_o = Signal(n_units, reset_less=True)
             self.stwd_mem_o = Signal(n_units, reset_less=True)
             self.addr_o = Signal(rwid, reset_less=True)
@@ -126,11 +126,13 @@ class CompUnitsBase(Elaboratable):
         issue_l = []
         busy_l = []
         req_rel_l = []
+        done_l = []
         rd_rel_l = []
         shadow_l = []
         godie_l = []
         for alu in self.units:
             req_rel_l.append(alu.req_rel_o)
+            done_l.append(alu.done_o)
             rd_rel_l.append(alu.rd_rel_o)
             shadow_l.append(alu.shadown_i)
             godie_l.append(alu.go_die_i)
@@ -140,6 +142,7 @@ class CompUnitsBase(Elaboratable):
             busy_l.append(alu.busy_o)
         comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
         comb += self.req_rel_o.eq(Cat(*req_rel_l))
+        comb += self.done_o.eq(Cat(*done_l))
         comb += self.busy_o.eq(Cat(*busy_l))
         comb += Cat(*godie_l).eq(self.go_die_i)
         comb += Cat(*shadow_l).eq(self.shadown_i)
@@ -610,13 +613,7 @@ class Scoreboard(Elaboratable):
         # Connect Picker
         #---------
         comb += intpick1.rd_rel_i[0:n_intfus].eq(cu.rd_rel_o[0:n_intfus])
-        #comb += intpick1.req_rel_i[0:n_intfus].eq(cu.req_rel_o[0:n_intfus])
-        # HACK for now: connect LD/ST request release to *address* release
-        comb += intpick1.req_rel_i[0].eq(cu.req_rel_o[0]) # ALU 0
-        comb += intpick1.req_rel_i[1].eq(cu.req_rel_o[1]) # ALU 1
-        comb += intpick1.req_rel_i[2].eq(cul.adr_rel_o[0]) # LD/ST 0
-        comb += intpick1.req_rel_i[3].eq(cul.adr_rel_o[1]) # LD/ST 1
-        comb += intpick1.req_rel_i[4].eq(cu.req_rel_o[4])  # BR 0
+        comb += intpick1.req_rel_i[0:n_intfus].eq(cu.done_o[0:n_intfus])
         int_rd_o = intfus.readable_o
         int_wr_o = intfus.writable_o
         comb += intpick1.readable_i[0:n_intfus].eq(int_rd_o[0:n_intfus])