invert Cat order, use 3 zeros (3 bits)

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 1c163bf060d78e85b15016b6364c93f743575b0f..2d4c175d683405e38010f666ad142dd9ea6b072b 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -80,8 +80,8 @@ class FPADD:
             with m.State("unpack"):
                     m.next = "special_cases"
                     m.d.sync += [
-                        a_m.eq(Cat(a[0:23], 0)),
-                        b_m.eq(Cat(b[0:23], 0)),
+                        a_m.eq(Cat(0, 0, 0, a[0:23])),
+                        b_m.eq(Cat(0, 0, 0, b[0:23])),
                         a_e.eq(Cat(a[23:31]) - 127),
                         b_e.eq(Cat(b[23:31]) - 127),
                         a_s.eq(Cat(a[31])),