configs: add option for memory channel intlv.
authorAdrian Herrera <adrian.herrera@arm.com>
Mon, 6 Apr 2020 12:53:03 +0000 (13:53 +0100)
committerAdrian Herrera <adrian.herrera@arm.com>
Thu, 9 Apr 2020 08:00:36 +0000 (08:00 +0000)
Current memory channel interleave is hard-coded to be maximum between 128
and system's cache line size. Making this value configurable enables use
cases with DMA masters accessing at higher than 128 block granularity.

Change-Id: I8123fa307efd3fd8f16c815ee74a84844bb51edb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27629
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

configs/common/MemConfig.py
configs/common/Options.py

index d1cc6558a08e7150397f287ac9ea33718daefe7e..9443520ae350005e928b63902c587929adb53f4c 100644 (file)
@@ -1,4 +1,4 @@
-# Copyright (c) 2013, 2017 ARM Limited
+# Copyright (c) 2013, 2017, 2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -109,6 +109,7 @@ def config_mem(options, system):
     opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
     opt_mem_ranks = getattr(options, "mem_ranks", None)
     opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
+    opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
 
     if opt_mem_type == "HMC_2500_1x32":
         HMChost = HMC.config_hmc_host_ctrl(options, system)
@@ -154,7 +155,7 @@ def config_mem(options, system):
     # byte granularity, or cache line granularity if larger than 128
     # byte. This value is based on the locality seen across a large
     # range of workloads.
-    intlv_size = max(128, system.cache_line_size.value)
+    intlv_size = max(opt_mem_channels_intlv, system.cache_line_size.value)
 
     # For every range (most systems will only have one), create an
     # array of controllers and set their parameters to match their
index 6c92f36d28c87f3657e6b6086414721b873a226d..6d0c6c295b55d548802278fa5c3aed1c3e015347 100644 (file)
@@ -1,4 +1,4 @@
-# Copyright (c) 2013-2019 ARM Limited
+# Copyright (c) 2013-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -110,6 +110,8 @@ def addNoISAOptions(parser):
                       help="Specify the physical memory size (single memory)")
     parser.add_option("--enable-dram-powerdown", action="store_true",
                        help="Enable low-power states in DRAMCtrl")
+    parser.add_option("--mem-channels-intlv", type="int",
+                      help="Memory channels interleave")
 
 
     parser.add_option("--memchecker", action="store_true")