remove trick of not setting SO

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 1ee3a4a01e18cd70c8fe57d7517f57cbfbb3dbfe..f054e3ec2613e912ebc005435c4c324079981d5a 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -32,10 +32,7 @@ class ALUOutputStage(CommonOutputStage):
 
         # copy overflow and sticky-overflow
         comb += self.o.xer_so.data.eq(self.so)
-        # SO is to be set - however to save regfile port requests, only set
-        # if the data actually changes. only possible due to pass-thru
-        with m.If(self.i.xer_so.data != self.so):
-            comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok)
+        comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok)
         comb += self.o.xer_ov.data.eq(ov)
         comb += self.o.xer_ov.ok.eq(op.oe.oe & op.oe.oe_ok) # OV/32 is to be set