add some debug checking to get_pdecode_cr_out

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 65da67413ca47399852ca1ecd737643d914d2c9f..4a4935f27c04216fbc3dc51edf5e1b8a84e8a7d6 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -370,12 +370,14 @@ def get_pdecode_cr_out(dec2, name):
     out_sel = yield op.cr_out
     out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
     sv_cr_out = yield op.sv_cr_out
+    spec = yield dec2.crout_svdec.spec
     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
     out = yield dec2.e.write_cr.data
     o_isvec = yield dec2.o_isvec
     print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
     print ("    sv_cr_out", sv_cr_out)
     print ("    cr_bf", out_bitfield)
+    print ("    spec", spec)
     # identify which regnames map to out / o2
     if name == 'CR0':
         if out_sel == CROutSel.CR0.value:

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 6cf06f34c677591e573d942d33272c30ded3ebf1..85f7b32d28cbdc3a271163f6cb7ca31b3fe92136 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -1071,6 +1071,9 @@ class PowerDecode2(PowerDecodeSubset):
         m.submodules.o_svdec = o_svdec = SVP64RegExtra()
         m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
 
+        # debug access to crout_svdec (used in get_pdecode_cr_out)
+        self.crout_svdec = crout_svdec
+
         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
         reg = Signal(5, reset_less=True)