whoops names changed in MMU FSM

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index f7541b8c48fbf7066fe07b3a43c618d21530f9de..1a3026e79e8e760822df1108edaabcb031c0e6a1 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -83,8 +83,8 @@ class FSMMMUStage(ControlBase):
         wb_out, wb_in = dcache.wb_out, dcache.wb_in
 
         # link ldst and MMU together
-        comb += l_in.eq(ldst.l_in)
-        comb += ldst.l_out.eq(l_out)
+        comb += l_in.eq(ldst.m_out)
+        comb += ldst.m_in.eq(l_out)
 
         data_i, data_o = self.p.data_i, self.n.data_o
         a_i, b_i, o, spr1_o = data_i.ra, data_i.rb, data_o.o, data_o.spr1