fix up syntax errors in power_decoder

diff --git a/src/decoder/power_decoder.py b/src/decoder/power_decoder.py
index 8c03c4e4c0fd5d8c0213a5eabbada9cf26ffd82e..213ab3e2fb7761f400ee2e830b159a6f9585c9db 100644 (file)
--- a/src/decoder/power_decoder.py
+++ b/src/decoder/power_decoder.py
@@ -24,17 +24,19 @@ class PowerOp:
 
     def _eq(self, row=None):
         if row is None:
-            row = {}
-        res = [self.function_unit.eq(Function[row.get('unit', Function.NONE)]),
-               self.internal_op.eq(InternalOp[row.get('internal op',
-                                                      InternalOp.OP_ILLEGAL)]),
-               self.in1_sel.eq(In1Sel[row.get('in1', 0)]),
-               self.in2_sel.eq(In2Sel[row.get('in2', 0)]),
-               self.in3_sel.eq(In3Sel[row.get('in3', 0)]),
-               self.out_sel.eq(OutSel[row.get('out', 0)]),
-               self.ldst_len.eq(LdstLen[row.get('ldst len', 0)]),
-               self.rc_sel.eq(RC[row.get('rc', 0)]),
-               self.cry_in.eq(CryIn[row.get('cry in', 0)]),
+            row = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
+                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
+                   'ldst len': 'NONE',
+                   'rc' : 'NONE', 'cry in' : 'ZERO'}
+        res = [self.function_unit.eq(Function[row['unit']]),
+               self.internal_op.eq(InternalOp[row['internal op']]),
+               self.in1_sel.eq(In1Sel[row['in1']]),
+               self.in2_sel.eq(In2Sel[row['in2']]),
+               self.in3_sel.eq(In3Sel[row['in3']]),
+               self.out_sel.eq(OutSel[row['out']]),
+               self.ldst_len.eq(LdstLen[row['ldst len']]),
+               self.rc_sel.eq(RC[row['rc']]),
+               self.cry_in.eq(CryIn[row['cry in']]),
                ]
         for bit in single_bit_flags:
             sig = getattr(self, get_signal_name(bit))

diff --git a/src/decoder/test/test_power_decoder.py b/src/decoder/test/test_power_decoder.py
index df85c6e88d319c84eb7038160d6a8b391a6f5323..582926856ceefb05d0037d348e7249117a887227 100644 (file)
--- a/src/decoder/test/test_power_decoder.py
+++ b/src/decoder/test/test_power_decoder.py
@@ -29,15 +29,15 @@ class DecoderTestCase(FHDLTestCase):
 
         m.submodules.dut = dut = PowerDecoder(width, csvname)
         comb += [dut.opcode_in.eq(opcode),
-                 function_unit.eq(dut.function_unit),
-                 in1_sel.eq(dut.in1_sel),
-                 in2_sel.eq(dut.in2_sel),
-                 in3_sel.eq(dut.in3_sel),
-                 out_sel.eq(dut.out_sel),
-                 rc_sel.eq(dut.rc_sel),
-                 ldst_len.eq(dut.ldst_len),
-                 cry_in.eq(dut.cry_in),
-                 internal_op.eq(dut.internal_op)]
+                 function_unit.eq(dut.op.function_unit),
+                 in1_sel.eq(dut.op.in1_sel),
+                 in2_sel.eq(dut.op.in2_sel),
+                 in3_sel.eq(dut.op.in3_sel),
+                 out_sel.eq(dut.op.out_sel),
+                 rc_sel.eq(dut.op.rc_sel),
+                 ldst_len.eq(dut.op.ldst_len),
+                 cry_in.eq(dut.op.cry_in),
+                 internal_op.eq(dut.op.internal_op)]
 
         sim = Simulator(m)
 
@@ -62,7 +62,7 @@ class DecoderTestCase(FHDLTestCase):
                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
                     self.assertEqual(enm(result), expected, msg)
                 for bit in single_bit_flags:
-                    sig = getattr(dut, get_signal_name(bit))
+                    sig = getattr(dut.op, get_signal_name(bit))
                     result = yield sig
                     expected = int(row[bit])
                     msg = f"{sig.name} == {result}, expected: {expected}"