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Fix import
author
Cesar Strauss
<cestrauss@gmail.com>
Mon, 15 Mar 2021 22:33:34 +0000
(19:33 -0300)
committer
Cesar Strauss
<cestrauss@gmail.com>
Mon, 15 Mar 2021 22:35:53 +0000
(19:35 -0300)
src/soc/decoder/power_svp64_rm.py
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diff --git
a/src/soc/decoder/power_svp64_rm.py
b/src/soc/decoder/power_svp64_rm.py
index d98c16ef40cea376d5a6bb062c7b118e5333fafb..bd1cd41601f6bfa68049df01405040c15cd097a0 100644
(file)
--- a/
src/soc/decoder/power_svp64_rm.py
+++ b/
src/soc/decoder/power_svp64_rm.py
@@
-20,7
+20,7
@@
from nmigen import Elaboratable, Module, Signal
from soc.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
SVP64PredMode, SVP64sat)
from soc.consts import EXTRA3
-from soc.svp64 import SVP64Rec
+from soc.sv
.sv
p64 import SVP64Rec
from nmutil.util import sel