missing yields in JTAG pads test to allow settling

diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py
index c2c273e0728eb50d831e7c4fa4cd603ff2a8ff87..25e2cdd457282b641eed6c18fb31040afb384aa0 100644 (file)
--- a/src/soc/debug/test/test_jtag_tap_srv.py
+++ b/src/soc/debug/test/test_jtag_tap_srv.py
@@ -73,6 +73,7 @@ def jtag_sim(dut, srv_dut):
 
     bs = yield from jtag_read_write_reg(dut, BS_SAMPLE, bslen, bs_actual)
     print ("bs scan", bin(bs))
+    yield
 
     print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
     print ("io1 core.o", (yield srv_dut.ios[1].core.o))