add in WishboneDownConvert into LoadStoreUnitInterface

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 8e581b5e8e1acdb2cd448a672b8d64cef2ba3715..d70655ffcf3e71312bc53f52bfcaa82328b65629 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -22,7 +22,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
         comb = m.d.comb
         m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
                                         features={'cti', 'bte', 'err'})
-        dbus = self.dbus
+        dbus = self.slavebus
 
         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
         # note: SRAM is a target (slave), dbus is initiator (master)

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index db05c3008946f585e380b725f2068276b136f6e0..de3246e90515548354e5de8b388c4b62b73bb0be 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -4,7 +4,9 @@ from nmigen.lib.fifo import SyncFIFO
 
 from soc.minerva.cache import L1Cache
 from soc.minerva.wishbone import make_wb_layout, WishboneArbiter, Cycle
+from soc.bus.wb_downconvert import WishboneDownConvert
 
+from copy import deepcopy
 
 __all__ = ["LoadStoreUnitInterface", "BareLoadStoreUnit",
            "CachedLoadStoreUnit"]
@@ -13,8 +15,13 @@ __all__ = ["LoadStoreUnitInterface", "BareLoadStoreUnit",
 class LoadStoreUnitInterface:
     def __init__(self, pspec):
         self.pspec = pspec
-        self.dbus = Record(make_wb_layout(pspec))
+        self.dbus = self.slavebus = Record(make_wb_layout(pspec))
         print(self.dbus.sel.shape())
+        if isinstance(pspec.wb_data_wid, int):
+            pspecslave = deepcopy(pspec)
+            pspecslave.data_wid = pspec.wb_data_wid
+            self.slavebus = Record(make_wb_layout(pspecslave))
+            self.cvt = WishboneDownConvert(self.dbus, self.slavebus)
         self.mask_wid = mask_wid = pspec.mask_wid
         self.addr_wid = addr_wid = pspec.addr_wid
         self.data_wid = data_wid = pspec.reg_wid
@@ -80,6 +87,9 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+        if hasattr(self, "cvt"):
+            m.submodules.cvt = cvt
+
         with m.If(self.dbus.cyc):
             with m.If(self.dbus.ack | self.dbus.err | ~self.m_valid_i):
                 m.d.sync += [