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different FreePDK45 experiments10 chip size
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 16:58:07 +0000 (16:58 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 16:58:07 +0000 (16:58 +0000)
experiments10_verilog/freepdk_c4m45/doDesign.py patch | blob | history

diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py
index 10dd423442818796ee0484b060975866561ade16..4acedc7a4aded19247b2ea86300c9d2dfec80fc5 100644 (file)
--- a/experiments10_verilog/freepdk_c4m45/doDesign.py
+++ b/experiments10_verilog/freepdk_c4m45/doDesign.py
@@ -31,8 +31,8 @@ def scriptMain ( **kw ):
     """The mandatory function to be called by Coriolis CGT/Unicorn."""
     global af
     rvalue = True
-    coreSize   = u(6*90.0)
-    chipBorder = u(2*214.0 + 10*13.0)
+    coreSize   = u(3*90.0)
+    chipBorder = u(4*214.0 + 10*13.0)
     try:
         helpers.setTraceLevel( 550 )
         cell, editor = plugins.kwParseMain( **kw )