// FlexBus External Signals
// AD inout bus separate for now in BSV
- interface Get#(Bit#(32)) m_AD; // out
- interface Put#(Bit#(32)) m_din; // in
+ interface Get#(Bit#(32)) AD; // out
+ interface Put#(Bit#(32)) din; // in
- interface Get#(Bit#(1)) m_R_Wn; // out
- interface Get#(Bit#(2)) m_TSIZ; // out
+ interface Get#(Bit#(1)) R_Wn; // out
+ interface Get#(Bit#(2)) TSIZ; // out
- interface Get#(Bit#(6)) m_FBCSn; // out
- interface Get#(Bit#(4)) m_BE_BWEn; // out
- interface Get#(Bit#(1)) m_TBSTn; // out
- interface Get#(Bit#(1)) m_OEn; // out
+ interface Get#(Bit#(6)) FBCSn; // out
+ interface Get#(Bit#(4)) BWEn; // out
+ interface Get#(Bit#(1)) TBSTn; // out
+ interface Get#(Bit#(1)) OEn; // out
- interface Get#(Bit#(1)) m_ALE; // out
- interface Put#(Bit#(1)) tAn; // in
+ interface Get#(Bit#(1)) ALE; // out
+ interface Put#(Bit#(1)) tAn; // in
endinterface: FlexBus_Master_IFC
endmethod
endinterface;
- interface m_din = interface Put
+ interface din = interface Put
method Action put(Bit#(32) in) if(c_din[0] matches tagged Invalid);
c_din[0] <= tagged Valid in;
endmethod
endinterface;
- interface m_AD = interface Get
+ interface AD = interface Get
method ActionValue#(Bit#(32)) get;
return r_AD;
endmethod
endinterface;
- interface m_R_Wn = interface Get
+ interface R_Wn = interface Get
method ActionValue#(Bit#(1)) get;
return r_R_Wn;
endmethod
endinterface;
- interface m_TSIZ = interface Get
+ interface TSIZ = interface Get
method ActionValue#(Bit#(2)) get;
return r_TSIZ;
endmethod
endinterface;
- interface m_FBCSn = interface Get
+ interface FBCSn = interface Get
method ActionValue#(Bit#(6)) get;
return r_FBCSn;
endmethod
endinterface;
- interface m_BE_BWEn = interface Get
+ interface BWEn = interface Get
method ActionValue#(Bit#(4)) get;
return r_BE_BWEn;
endmethod
endinterface;
- interface m_TBSTn = interface Get
+ interface TBSTn = interface Get
method ActionValue#(Bit#(1)) get;
return r_TBSTn;
endmethod
endinterface;
- interface m_OEn = interface Get
+ interface OEn = interface Get
method ActionValue#(Bit#(1)) get;
return r_OEn;
endmethod
endinterface;
- interface m_ALE = interface Get
+ interface ALE = interface Get
method ActionValue#(Bit#(1)) get;
return r_ALE;
endmethod
WORKING_DIR := $(shell pwd)
BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
-BSVINCDIR:= $(BSVINCDIR):../../../src/uncore/axi4
-BSVINCDIR:= $(BSVINCDIR):../../../src/uncore/axi4lite
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/gpio
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/rgbttl
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/i2c
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/mux
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/plic
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/pwm
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/qspi
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/spi
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/sdmmc
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/uart
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite
+BSVINCDIR:= $(BSVINCDIR):./test
default: gen_verilog