missed valid/ready_i/o to o/i_ conversion

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 293682e3a12da7d36e865b41e0ebbd87b082a382..7c323ba1d208013ccdeeb7d1a2118a4f94a2de37 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -89,18 +89,18 @@ class TestRunner(FHDLTestCase):
             yield from set_alu_inputs(alu, pdecode2, simulator)
 
             # set valid for one cycle, propagate through pipeline...
-            yield alu.p.valid_i.eq(1)
+            yield alu.p.i_valid.eq(1)
             yield
-            yield alu.p.valid_i.eq(0)
+            yield alu.p.i_valid.eq(0)
 
             opname = code.split(' ')[0]
             yield from simulator.call(opname)
             index = simulator.pc.CIA.value//4
 
-            vld = yield alu.n.valid_o
+            vld = yield alu.n.o_valid
             while not vld:
                 yield
-                vld = yield alu.n.valid_o
+                vld = yield alu.n.o_valid
             yield
 
             yield from self.check_alu_outputs(alu, pdecode2,
@@ -120,7 +120,7 @@ class TestRunner(FHDLTestCase):
         m.submodules.alu = alu = LogicalBasePipe(pspec)
 
         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
-        comb += alu.n.ready_i.eq(1)
+        comb += alu.n.i_ready.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)