r600g: add initial evergreen support
authorDave Airlie <airlied@redhat.com>
Fri, 3 Sep 2010 04:38:41 +0000 (14:38 +1000)
committerDave Airlie <airlied@redhat.com>
Fri, 10 Sep 2010 09:41:18 +0000 (19:41 +1000)
adds shader opcodes + assembler support (except ARL)
uses constant buffers
add interp instructions in fragment shader
adds all evergreen hw states
adds evergreen pm4 support.

this runs gears for me on my evergreen

25 files changed:
src/gallium/drivers/r600/Makefile
src/gallium/drivers/r600/eg_asm.c [new file with mode: 0644]
src/gallium/drivers/r600/eg_hw_states.c [new file with mode: 0644]
src/gallium/drivers/r600/eg_sq.h [new file with mode: 0644]
src/gallium/drivers/r600/eg_state_inlines.h [new file with mode: 0644]
src/gallium/drivers/r600/eg_states_inc.h [new file with mode: 0644]
src/gallium/drivers/r600/evergreend.h [new file with mode: 0644]
src/gallium/drivers/r600/r600_asm.c
src/gallium/drivers/r600/r600_asm.h
src/gallium/drivers/r600/r600_context.c
src/gallium/drivers/r600/r600_context.h
src/gallium/drivers/r600/r600_hw_states.c
src/gallium/drivers/r600/r600_opcodes.h
src/gallium/drivers/r600/r600_screen.c
src/gallium/drivers/r600/r600_shader.c
src/gallium/drivers/r600/r600_sq.h
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/r600/r600_texture.c
src/gallium/drivers/r600/r700_asm.c
src/gallium/drivers/r600/radeon.h
src/gallium/winsys/r600/drm/eg_states.h [new file with mode: 0644]
src/gallium/winsys/r600/drm/gen_eg_states.py [new file with mode: 0644]
src/gallium/winsys/r600/drm/r600_state.c
src/gallium/winsys/r600/drm/r600d.h
src/gallium/winsys/r600/drm/radeon.c

index 707c2fd0f4faeec093d46c9035ba39cd630d5e84..a5249e09aa3ef8f8a5aee318120181396b956beb 100644 (file)
@@ -20,6 +20,8 @@ C_SOURCES = \
        r600_texture.c \
        r600_asm.c \
        r700_asm.c \
-       r600_hw_states.c
+       r600_hw_states.c \
+       eg_asm.c \
+       eg_hw_states.c
 
 include ../../Makefile.template
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
new file mode 100644 (file)
index 0000000..bc5dda4
--- /dev/null
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "r600_asm.h"
+#include "r600_context.h"
+#include "util/u_memory.h"
+#include "eg_sq.h"
+#include "r600_opcodes.h"
+#include <stdio.h>
+#include <errno.h>
+
+int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
+{
+       unsigned id = cf->id;
+
+       switch (cf->inst) {
+       case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
+       case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
+               bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
+                 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode);
+               bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
+                                       S_SQ_CF_ALU_WORD1_BARRIER(1) |
+                                       S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
+               break;
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+               bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
+               bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
+                                       S_SQ_CF_WORD1_BARRIER(1) |
+                                       S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
+               break;
+       case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+       case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+               bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
+               bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
+                       S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
+               break;
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+               bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
+               bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
+                                       S_SQ_CF_WORD1_BARRIER(1) |
+                                       S_SQ_CF_WORD1_COND(cf->cond) |
+                                       S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
+
+               break;
+       default:
+               R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
+               return -EINVAL;
+       }
+       return 0;
+}
diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
new file mode 100644 (file)
index 0000000..9e704f0
--- /dev/null
@@ -0,0 +1,1071 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *           2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ *      Dave Airlie
+ */
+#include <util/u_inlines.h>
+#include <util/u_format.h>
+#include <util/u_memory.h>
+#include <util/u_blitter.h>
+#include "util/u_pack_color.h"
+#include "r600_screen.h"
+#include "r600_context.h"
+#include "r600_resource.h"
+#include "eg_state_inlines.h"
+#include "evergreend.h"
+
+#include "eg_states_inc.h"
+
+static void eg_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       int i;
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
+       rstate->states[EG_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
+       rstate->states[EG_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
+       rstate->states[EG_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
+       rstate->states[EG_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
+       rstate->states[EG_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
+       rstate->states[EG_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
+       rstate->states[EG_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
+       rstate->states[EG_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
+       rstate->states[EG_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
+       rstate->states[EG_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
+       rstate->states[EG_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
+       rstate->states[EG_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
+
+       for (i = 0; i < 8; i++) {
+               unsigned eqRGB = state->rt[i].rgb_func;
+               unsigned srcRGB = state->rt[i].rgb_src_factor;
+               unsigned dstRGB = state->rt[i].rgb_dst_factor;
+               
+               unsigned eqA = state->rt[i].alpha_func;
+               unsigned srcA = state->rt[i].alpha_src_factor;
+               unsigned dstA = state->rt[i].alpha_dst_factor;
+               uint32_t bc = 0;
+
+               if (!state->rt[i].blend_enable)
+                       continue;
+
+               bc |= S_028780_BLEND_CONTROL_ENABLE(1);
+
+               bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+               bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+               bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
+
+               if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+                       bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
+                       bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+                       bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+                       bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
+               }
+
+               rstate->states[EG_BLEND__CB_BLEND0_CONTROL + i] = bc;
+       }
+
+       radeon_state_pm4(rstate);
+}
+
+static void eg_ucp(struct r600_context *rctx, struct radeon_state *rstate,
+           const struct pipe_clip_state *state)
+{
+       struct r600_screen *rscreen = rctx->screen;
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
+
+       for (int i = 0; i < state->nr; i++) {
+               rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
+               rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
+               rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
+               rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
+       }
+       radeon_state_pm4(rstate);
+}
+
+static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
+                       const struct pipe_framebuffer_state *state, int cb)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       struct r600_resource_texture *rtex;
+       struct r600_resource *rbuffer;
+       unsigned level = state->cbufs[cb]->level;
+       unsigned pitch, slice;
+       unsigned color_info;
+       unsigned format, swap, ntype;
+       const struct util_format_description *desc;
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
+       rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+       rbuffer = &rtex->resource;
+       rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+       rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+       rstate->nbo = 1;
+       pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+       slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+
+       ntype = 0;
+       desc = util_format_description(rtex->resource.base.b.format);
+       if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+               ntype = V_028C70_NUMBER_SRGB;
+
+       format = r600_translate_colorformat(rtex->resource.base.b.format);
+       swap = r600_translate_colorswap(rtex->resource.base.b.format);
+
+       color_info = S_028C70_FORMAT(format) |
+               S_028C70_COMP_SWAP(swap) |
+               S_028C70_BLEND_CLAMP(1) |
+               S_028C70_SOURCE_FORMAT(1) |
+               S_028C70_NUMBER_TYPE(ntype);
+
+       rstate->states[EG_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
+       rstate->states[EG_CB0__CB_COLOR0_INFO] = color_info;
+       rstate->states[EG_CB0__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
+       rstate->states[EG_CB0__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
+       rstate->states[EG_CB0__CB_COLOR0_VIEW] = 0x00000000;
+       rstate->states[EG_CB0__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
+
+       radeon_state_pm4(rstate);
+}
+
+static void eg_db(struct r600_context *rctx, struct radeon_state *rstate,
+                       const struct pipe_framebuffer_state *state)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       struct r600_resource_texture *rtex;
+       struct r600_resource *rbuffer;
+       unsigned level;
+       unsigned pitch, slice, format;
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
+       if (state->zsbuf == NULL)
+               return;
+
+       rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+       rtex->tilled = 1;
+       rtex->array_mode = 2;
+       rtex->tile_type = 1;
+       rtex->depth = 1;
+       rbuffer = &rtex->resource;
+
+       rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+       rstate->nbo = 1;
+       rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+       level = state->zsbuf->level;
+       pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+       slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+       format = r600_translate_dbformat(state->zsbuf->texture->format);
+       rstate->states[EG_DB__DB_HTILE_DATA_BASE] = state->zsbuf->offset >> 8;
+       rstate->states[EG_DB__DB_Z_READ_BASE] = state->zsbuf->offset >> 8;
+       rstate->states[EG_DB__DB_Z_WRITE_BASE] = state->zsbuf->offset >> 8;
+       rstate->states[EG_DB__DB_STENCIL_READ_BASE] = state->zsbuf->offset >> 8;
+       rstate->states[EG_DB__DB_STENCIL_WRITE_BASE] = state->zsbuf->offset >> 8;
+       rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format);
+       rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
+       rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
+       rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
+       radeon_state_pm4(rstate);
+}
+
+static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
+{
+       const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
+       const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+       const struct pipe_clip_state *clip = NULL;
+       struct r600_screen *rscreen = rctx->screen;
+       float offset_units = 0, offset_scale = 0;
+       char depth = 0;
+       unsigned offset_db_fmt_cntl = 0;
+       unsigned tmp;
+       unsigned prov_vtx = 1;
+
+       if (rctx->clip)
+               clip = &rctx->clip->state.clip;
+       if (fb->zsbuf) {
+               offset_units = state->offset_units;
+               offset_scale = state->offset_scale * 12.0f;
+               switch (fb->zsbuf->texture->format) {
+               case PIPE_FORMAT_Z24X8_UNORM:
+               case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+                       depth = -24;
+                       offset_units *= 2.0f;
+                       break;
+               case PIPE_FORMAT_Z32_FLOAT:
+                       depth = -23;
+                       offset_units *= 1.0f;
+                       offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+                       break;
+               case PIPE_FORMAT_Z16_UNORM:
+                       depth = -16;
+                       offset_units *= 4.0f;
+                       break;
+               default:
+                       R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
+                       return;
+               }
+       }
+       offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
+
+       if (state->flatshade_first)
+               prov_vtx = 0;
+
+       rctx->flat_shade = state->flatshade;
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
+       rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000000;
+       if (rctx->flat_shade)
+               rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_FLAT_SHADE_ENA(1);
+       if (state->sprite_coord_enable) {
+               rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
+                               S_0286D4_PNT_SPRITE_ENA(1) |
+                               S_0286D4_PNT_SPRITE_OVRD_X(2) |
+                               S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+                               S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+                               S_0286D4_PNT_SPRITE_OVRD_W(1);
+               if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+                       rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
+                                       S_0286D4_PNT_SPRITE_TOP_1(1);
+               }
+       }
+       rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
+       if (clip) {
+               rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
+               rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
+               rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
+       }
+       rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] =
+               S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+               S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+               S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+               S_028814_FACE(!state->front_ccw) |
+               S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+               S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+               S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
+       rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] =
+                       S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+                       S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
+       rstate->states[EG_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
+       /* point size 12.4 fixed point */
+       tmp = (unsigned)(state->point_size * 8.0);
+       rstate->states[EG_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
+       rstate->states[EG_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
+       rstate->states[EG_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
+       rstate->states[EG_RASTERIZER__PA_SU_VTX_CNTL] = 0x00000005;
+
+       rstate->states[EG_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
+       rstate->states[EG_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
+       rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
+       rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
+       rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
+       rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
+       rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
+       rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
+       rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
+       rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
+       rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
+       rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
+       radeon_state_pm4(rstate);
+}
+
+static void eg_scissor(struct r600_context *rctx, struct radeon_state *rstate)
+{
+       const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
+       const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+       struct r600_screen *rscreen = rctx->screen;
+       unsigned minx, maxx, miny, maxy;
+       u32 tl, br;
+
+       if (state == NULL) {
+               minx = 0;
+               miny = 0;
+               maxx = fb->cbufs[0]->width;
+               maxy = fb->cbufs[0]->height;
+       } else {
+               minx = state->minx;
+               miny = state->miny;
+               maxx = state->maxx;
+               maxy = state->maxy;
+       }
+       tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny);
+       br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
+       /* screen scissor has no WINDOW OFFSET */
+       rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
+       rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
+       rstate->states[EG_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
+       rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl | S_028204_WINDOW_OFFSET_DISABLE(1);
+       rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
+       rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
+       rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
+       rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
+       rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
+       rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
+       radeon_state_pm4(rstate);
+}
+
+static void eg_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
+{
+       struct r600_screen *rscreen = rctx->screen;
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
+       rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
+       rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
+       rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+       radeon_state_pm4(rstate);
+}
+
+static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
+{
+       const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
+       const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
+       struct r600_screen *rscreen = rctx->screen;
+       unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+       unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+       struct r600_shader *rshader;
+       struct r600_query *rquery;
+       boolean query_running;
+       int i;
+
+       if (rctx->ps_shader == NULL) {
+               return;
+       }
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
+
+       db_shader_control = 0x210;
+       rshader = &rctx->ps_shader->shader;
+       if (rshader->uses_kill)
+               db_shader_control |= (1 << 6);
+       for (i = 0; i < rshader->noutput; i++) {
+               if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+                       db_shader_control |= 1;
+       }
+       stencil_ref_mask = 0;
+       stencil_ref_mask_bf = 0;
+       db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+               S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+               S_028800_ZFUNC(state->depth.func);
+       /* set stencil enable */
+
+       if (state->stencil[0].enabled) {
+               db_depth_control |= S_028800_STENCIL_ENABLE(1);
+               db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+               db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+               db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+               db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+
+               stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+                       S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+               stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
+               if (state->stencil[1].enabled) {
+                       db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+                       db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+                       db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+                       db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+                       db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+                       stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+                               S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+                       stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
+               }
+       }
+
+       alpha_test_control = 0;
+       alpha_ref = 0;
+       if (state->alpha.enabled) {
+               alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+               alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+               alpha_ref = fui(state->alpha.ref_value);
+       }
+
+       db_render_control = 0;
+///    db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
+///            S_028D0C_DEPTH_COMPRESS_DISABLE(1);
+       db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
+               S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
+               S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
+
+       query_running = false;
+
+       LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+               if (rquery->state & R600_QUERY_STATE_STARTED) {
+                       query_running = true;
+               }
+       }
+
+       if (query_running) {
+               db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
+               if (rscreen->chip_class == R700)
+                       db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
+       }
+
+       rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
+       rstate->states[EG_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
+       rstate->states[EG_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
+       rstate->states[EG_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
+       rstate->states[EG_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
+       rstate->states[EG_DSA__SX_ALPHA_REF] = alpha_ref;
+       //      rstate->states[EG_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
+       //      rstate->states[EG_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
+       rstate->states[EG_DSA__SPI_FOG_CNTL] = 0x00000000;
+       rstate->states[EG_DSA__DB_DEPTH_CONTROL] = db_depth_control;
+       rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
+       rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
+       rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
+         
+       rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
+       rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
+       rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
+       radeon_state_pm4(rstate);
+}
+
+
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+       return value * (1 << frac_bits);
+}
+
+static void eg_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
+                               const struct pipe_sampler_state *state, unsigned id)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       union util_color uc;
+
+       util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
+       if (uc.ui) {
+               rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
+               rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
+               rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
+               rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
+       }
+       radeon_state_pm4(rstate);
+}
+
+static void eg_sampler(struct r600_context *rctx, struct radeon_state *rstate,
+                       const struct pipe_sampler_state *state, unsigned id)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       union util_color uc;
+
+       util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
+       rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
+                       S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+                       S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+                       S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+                       S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+                       S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+                       S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+                       S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
+                       S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
+       /* FIXME LOD it depends on texture base level ... */
+       rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
+                       S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+               S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6));
+
+       rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = 
+               S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
+S_03C008_TYPE(1);
+       radeon_state_pm4(rstate);
+
+}
+
+
+static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
+                       const struct pipe_sampler_view *view, unsigned id)
+{
+       struct r600_context *rctx = r600_context(ctx);
+       struct r600_screen *rscreen = rctx->screen;
+       const struct util_format_description *desc;
+       struct r600_resource_texture *tmp;
+       struct r600_resource *rbuffer;
+       unsigned format;
+       uint32_t word4 = 0, yuv_format = 0, pitch = 0;
+       unsigned char swizzle[4];
+       int r;
+
+       rstate->cpm4 = 0;
+       swizzle[0] = view->swizzle_r;
+       swizzle[1] = view->swizzle_g;
+       swizzle[2] = view->swizzle_b;
+       swizzle[3] = view->swizzle_a;
+       format = r600_translate_texformat(view->texture->format,
+                                         swizzle,
+                                         &word4, &yuv_format);
+       if (format == ~0) {
+               return;
+       }
+       desc = util_format_description(view->texture->format);
+       if (desc == NULL) {
+               R600_ERR("unknow format %d\n", view->texture->format);
+               return;
+       }
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
+       tmp = (struct r600_resource_texture*)view->texture;
+       rbuffer = &tmp->resource;
+       if (tmp->depth) {
+               r = r600_texture_from_depth(ctx, tmp, view->first_level);
+               if (r) {
+                       return;
+               }
+               rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+               rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+       } else {
+               rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+       }
+       rstate->nbo = 2;
+       rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+       rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
+       rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+       rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
+
+       pitch = (tmp->pitch[0] / tmp->bpt);
+       pitch = (pitch + 0x7) & ~0x7;
+
+       /* FIXME properly handle first level != 0 */
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] =
+                       S_030000_DIM(r600_tex_dim(view->texture->target)) |
+                       S_030000_PITCH((pitch / 8) - 1) |
+                       S_030000_TEX_WIDTH(view->texture->width0 - 1);
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD1] =
+               S_030004_TEX_HEIGHT(view->texture->height0 - 1) |
+               S_030004_TEX_DEPTH(view->texture->depth0 - 1);
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD4] =
+                       word4 | 
+                       S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
+                       S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
+                       S_030010_REQUEST_SIZE(1) |
+                       S_030010_BASE_LEVEL(view->first_level);
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD5] =
+                       S_030014_LAST_LEVEL(view->last_level) |
+                       S_030014_BASE_ARRAY(0) |
+                       S_030014_LAST_ARRAY(0);
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0;
+       rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD7] =
+                       S_03001C_DATA_FORMAT(format) |
+                       S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE);
+       radeon_state_pm4(rstate);
+}
+
+static void eg_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
+       int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
+       uint32_t color_control, target_mask, shader_mask;
+       int i;
+
+       target_mask = 0;
+       shader_mask = 0;
+       color_control = S_028808_MODE(1);
+
+       for (i = 0; i < nr_cbufs; i++) {
+               shader_mask |= 0xf << (i * 4);
+       }
+
+       if (pbs->logicop_enable) {
+               color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
+       } else {
+               color_control |= (0xcc << 16);
+       }
+
+       if (pbs->independent_blend_enable) {
+               for (i = 0; i < nr_cbufs; i++) {
+                       target_mask |= (pbs->rt[i].colormask << (4 * i));
+               }
+       } else {
+               for (i = 0; i < nr_cbufs; i++) {
+                       target_mask |= (pbs->rt[0].colormask << (4 * i));
+               }
+       }
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
+       rstate->states[EG_CB_CNTL__CB_SHADER_MASK] = shader_mask;
+       rstate->states[EG_CB_CNTL__CB_TARGET_MASK] = target_mask;
+       rstate->states[EG_CB_CNTL__CB_COLOR_CONTROL] = color_control;
+       rstate->states[EG_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
+       rstate->states[EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
+       rstate->states[EG_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
+       radeon_state_pm4(rstate);
+}
+
+
+static void eg_init_config(struct r600_context *rctx)
+{
+       int ps_prio;
+       int vs_prio;
+       int gs_prio;
+       int es_prio;
+       int hs_prio, cs_prio, ls_prio;
+       int num_ps_gprs;
+       int num_vs_gprs;
+       int num_gs_gprs;
+       int num_es_gprs;
+       int num_hs_gprs;
+       int num_ls_gprs;
+       int num_temp_gprs;
+       int num_ps_threads;
+       int num_vs_threads;
+       int num_gs_threads;
+       int num_es_threads;
+       int num_hs_threads;
+       int num_ls_threads;
+       int num_ps_stack_entries;
+       int num_vs_stack_entries;
+       int num_gs_stack_entries;
+       int num_es_stack_entries;
+       int num_hs_stack_entries;
+       int num_ls_stack_entries;
+       enum radeon_family family;
+
+       family = radeon_get_family(rctx->rw);
+       ps_prio = 0;
+       vs_prio = 1;
+       gs_prio = 2;
+       es_prio = 3;
+       hs_prio = 0;
+       ls_prio = 0;
+       cs_prio = 0;
+
+       switch (family) {
+       case CHIP_CEDAR:
+       default:
+               num_ps_gprs = 93;
+               num_vs_gprs = 46;
+               num_temp_gprs = 4;
+               num_gs_gprs = 31;
+               num_es_gprs = 31;
+               num_hs_gprs = 23;
+               num_ls_gprs = 23;
+               num_ps_threads = 96;
+               num_vs_threads = 16;
+               num_gs_threads = 16;
+               num_es_threads = 16;
+               num_hs_threads = 16;
+               num_ls_threads = 16;
+               num_ps_stack_entries = 42;
+               num_vs_stack_entries = 42;
+               num_gs_stack_entries = 42;
+               num_es_stack_entries = 42;
+               num_hs_stack_entries = 42;
+               num_ls_stack_entries = 42;
+               break;
+       case CHIP_REDWOOD:
+               num_ps_gprs = 93;
+               num_vs_gprs = 46;
+               num_temp_gprs = 4;
+               num_gs_gprs = 31;
+               num_es_gprs = 31;
+               num_hs_gprs = 23;
+               num_ls_gprs = 23;
+               num_ps_threads = 128;
+               num_vs_threads = 20;
+               num_gs_threads = 20;
+               num_es_threads = 20;
+               num_hs_threads = 20;
+               num_ls_threads = 20;
+               num_ps_stack_entries = 42;
+               num_vs_stack_entries = 42;
+               num_gs_stack_entries = 42;
+               num_es_stack_entries = 42;
+               num_hs_stack_entries = 42;
+               num_ls_stack_entries = 42;
+               break;
+       case CHIP_JUNIPER:
+               num_ps_gprs = 93;
+               num_vs_gprs = 46;
+               num_temp_gprs = 4;
+               num_gs_gprs = 31;
+               num_es_gprs = 31;
+               num_hs_gprs = 23;
+               num_ls_gprs = 23;
+               num_ps_threads = 128;
+               num_vs_threads = 20;
+               num_gs_threads = 20;
+               num_es_threads = 20;
+               num_hs_threads = 20;
+               num_ls_threads = 20;
+               num_ps_stack_entries = 85;
+               num_vs_stack_entries = 85;
+               num_gs_stack_entries = 85;
+               num_es_stack_entries = 85;
+               num_hs_stack_entries = 85;
+               num_ls_stack_entries = 85;
+               break;
+       case CHIP_CYPRESS:
+       case CHIP_HEMLOCK:
+               num_ps_gprs = 93;
+               num_vs_gprs = 46;
+               num_temp_gprs = 4;
+               num_gs_gprs = 31;
+               num_es_gprs = 31;
+               num_hs_gprs = 23;
+               num_ls_gprs = 23;
+               num_ps_threads = 128;
+               num_vs_threads = 20;
+               num_gs_threads = 20;
+               num_es_threads = 20;
+               num_hs_threads = 20;
+               num_ls_threads = 20;
+               num_ps_stack_entries = 85;
+               num_vs_stack_entries = 85;
+               num_gs_stack_entries = 85;
+               num_es_stack_entries = 85;
+               num_hs_stack_entries = 85;
+               num_ls_stack_entries = 85;
+               break;
+       }
+
+       radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
+
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] = 0x00000000;
+       switch (family) {
+       case CHIP_CEDAR:
+               break;
+       default:
+               rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+               break;
+       }
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_EXPORT_SRC_C(1);
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_CS_PRIO(cs_prio);
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_LS_PRIO(ls_prio);
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_HS_PRIO(hs_prio);
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+       rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_ES_GPRS(num_es_gprs);
+
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] = 0;
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
+       rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
+
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] = 0;
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_PS_THREADS(num_ps_threads);
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_VS_THREADS(num_vs_threads);
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_GS_THREADS(num_gs_threads);
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_ES_THREADS(num_es_threads);
+
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] = 0;
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
+       rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
+
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] = 0;
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
+       rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
+
+       rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL_1] = S_00913C_VTX_DONE_DELAY(4);
+
+       rctx->config.states[EG_CONFIG__SX_MISC] = 0x00000000;
+
+       rctx->config.states[EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
+       rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_0] = 0x0;
+       rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_1] = 0x0;
+
+       rctx->config.states[EG_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+
+       rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2] = 0x00000000;
+       rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3] = 0x00000000;
+
+       rctx->config.states[EG_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_GS_MODE] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_STRMOUT_CONFIG] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG] = 0x00000000;
+       rctx->config.states[EG_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+       rctx->config.states[EG_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+//     rctx->config.states[EG_CONFIG__VGT_CACHE_INVALIDATION] = 0x2;
+//     rctx->config.states[EG_CONFIG__VGT_GS_VERTEX_REUSE] = 0x16;
+       rctx->config.states[EG_CONFIG__PA_CL_ENHANCE] = (3 << 1) | 1;
+       
+       radeon_state_pm4(&rctx->config);
+}
+
+static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
+                           uint32_t stride, uint32_t format)
+{
+       struct radeon_state *vs_resource = &rctx->vs_resource[id];
+       struct r600_screen *rscreen = rctx->screen;
+
+       radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
+       vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+       vs_resource->nbo = 1;
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) |
+               S_030008_DATA_FORMAT(format);
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+               S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+               S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+               S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
+         
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0x00000000;
+       vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = 0xC0000000;
+       vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
+       vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
+       return radeon_state_pm4(vs_resource);
+}
+
+static int eg_draw_vgt_init(struct r600_context *rctx, struct radeon_state *draw,
+                           struct r600_resource *rbuffer,
+                           uint32_t count, int vgt_draw_initiator)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       
+       radeon_state_init(draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
+       draw->states[EG_DRAW__VGT_NUM_INDICES] = count;
+       draw->states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
+       if (rbuffer) {
+               draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
+               draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
+               draw->nbo = 1;
+       }
+       return radeon_state_pm4(draw);
+}
+
+static int eg_draw_vgt_prim(struct r600_context *rctx, struct radeon_state *vgt,
+                           uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       radeon_state_init(vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
+       vgt->states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim;
+       vgt->states[EG_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+       vgt->states[EG_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
+       vgt->states[EG_VGT__VGT_INDX_OFFSET] = start;
+       vgt->states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+       vgt->states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
+       vgt->states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+       vgt->states[EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+       vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+       vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
+       return radeon_state_pm4(vgt);
+}
+
+
+static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
+                         struct radeon_state *state)
+{
+       struct r600_screen *rscreen = rctx->screen;
+       const struct pipe_rasterizer_state *rasterizer;
+       struct r600_shader *rshader = &rpshader->shader;
+       unsigned i, tmp, exports_ps, num_cout;
+       boolean have_pos = FALSE;
+
+       rasterizer = &rctx->rasterizer->state.rasterizer;
+
+       radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
+       for (i = 0; i < rshader->ninput; i++) {
+               tmp = S_028644_SEMANTIC(i);
+               tmp |= S_028644_SEL_CENTROID(1);
+               if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+                       have_pos = TRUE;
+               if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+                   rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+                   rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+                       tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+               }
+               if (rasterizer->sprite_coord_enable & (1 << i)) {
+                       tmp |= S_028644_PT_SPRITE_TEX(1);
+               }
+               state->states[EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
+       }
+
+       exports_ps = 0;
+       num_cout = 0;
+       for (i = 0; i < rshader->noutput; i++) {
+               if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+                       exports_ps |= 1;
+               else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+                       exports_ps |= (1 << (num_cout+1));
+                       num_cout++;
+               }
+       }
+       if (!exports_ps) {
+               /* always at least export 1 component per pixel */
+               exports_ps = 2;
+       }
+       state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
+                                                       S_0286CC_PERSP_GRADIENT_ENA(1);
+       if (have_pos) {
+               state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1);
+               state->states[EG_PS_SHADER__SPI_INPUT_Z] |= 1;
+       }
+       state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
+       state->states[EG_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028844_NUM_GPRS(rshader->bc.ngpr) | S_028844_PRIME_CACHE_ON_DRAW(1) |
+               S_028844_STACK_SIZE(rshader->bc.nstack);
+       state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
+       state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) |
+         S_0286E0_LINEAR_CENTROID_ENA(1); 
+       state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+       state->nbo = 1;
+       state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+       return radeon_state_pm4(state);
+}
+
+static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
+                         struct radeon_state *state)
+{
+       struct r600_screen *rscreen = rctx->screen;     
+       struct r600_shader *rshader = &rpshader->shader;
+       unsigned i, tmp;
+
+       radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
+       for (i = 0; i < 10; i++) {
+               state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
+       }
+       /* so far never got proper semantic id from tgsi */
+       for (i = 0; i < 32; i++) {
+               tmp = i << ((i & 3) * 8);
+               state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
+       }
+       state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
+       state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) |
+               S_028860_STACK_SIZE(rshader->bc.nstack);
+       state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+       state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+       state->nbo = 2;
+       state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+       state->placement[2] = RADEON_GEM_DOMAIN_GTT;
+       return radeon_state_pm4(state);
+}
+
+struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
+       .blend = eg_blend,
+       .ucp = eg_ucp,
+       .cb = eg_cb,
+       .db = eg_db,
+       .rasterizer = eg_rasterizer,
+       .scissor = eg_scissor,
+       .viewport = eg_viewport,
+       .dsa = eg_dsa,
+       .sampler_border = eg_sampler_border,
+       .sampler = eg_sampler,
+       .resource = eg_resource,
+       .cb_cntl = eg_cb_cntl,
+       .vs_resource = eg_vs_resource,
+       .vgt_init = eg_draw_vgt_init,
+       .vgt_prim = eg_draw_vgt_prim,
+       .vs_shader = eg_vs_shader,
+       .ps_shader = eg_ps_shader,
+       .init_config = eg_init_config,
+};
+
+void eg_set_constant_buffer(struct pipe_context *ctx,
+                           uint shader, uint index,
+                           struct pipe_resource *buffer)
+{
+       struct r600_screen *rscreen = r600_screen(ctx->screen);
+       struct r600_context *rctx = r600_context(ctx);
+       unsigned nconstant = 0, type, shader_class, size;
+       struct radeon_state *rstate, *rstates;
+       struct r600_resource *rbuffer = (struct r600_resource*)buffer;
+
+       type = R600_STATE_CBUF;
+
+       switch (shader) {
+       case PIPE_SHADER_VERTEX:
+               shader_class = R600_SHADER_VS;
+               rstates = rctx->vs_constant;
+               break;
+       case PIPE_SHADER_FRAGMENT:
+               shader_class = R600_SHADER_PS;
+               rstates = rctx->ps_constant;
+               break;
+       default:
+               R600_ERR("unsupported %d\n", shader);
+               return;
+       }
+
+       rstate = &rstates[0];
+
+#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
+       nconstant = buffer->width0 / 16;
+       size = ALIGN_DIVUP(nconstant, 16);
+
+       radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
+       rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
+       rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
+
+       rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+       rstate->nbo = 1;
+       rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+       if (radeon_state_pm4(rstate))
+               return;
+       radeon_draw_bind(&rctx->draw, rstate);
+}
diff --git a/src/gallium/drivers/r600/eg_sq.h b/src/gallium/drivers/r600/eg_sq.h
new file mode 100644 (file)
index 0000000..f80e8bd
--- /dev/null
@@ -0,0 +1,485 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef EG_SQ_H
+#define EG_SQ_H
+
+#define P_SQ_CF_WORD0
+#define   S_SQ_CF_WORD0_ADDR(x)                                      (((x) & 0xFFFFFF) << 0)
+#define   G_SQ_CF_WORD0_ADDR(x)                                      (((x) >> 0) & 0xFFFFFF)
+#define   C_SQ_CF_WORD0_ADDR                                         0x00000000
+#define   S_SQ_CF_WORD0_JUMPTABLE_SEL(x)                             (((x) & 0x7) << 24)
+#define   G_SQ_CF_WORD0_JUMPTABLE_SEL(x)                             (((x) >> 24) & 0x7)
+#define   C_SQ_CF_WORD0_JUMPTABLE_SEL                                0xF8FFFFFF
+#define P_SQ_CF_WORD1
+#define   S_SQ_CF_WORD1_POP_COUNT(x)                                 (((x) & 0x7) << 0)
+#define   G_SQ_CF_WORD1_POP_COUNT(x)                                 (((x) >> 0) & 0x7)
+#define   C_SQ_CF_WORD1_POP_COUNT                                    0xFFFFFFF8
+#define   S_SQ_CF_WORD1_CF_CONST(x)                                  (((x) & 0x1F) << 3)
+#define   G_SQ_CF_WORD1_CF_CONST(x)                                  (((x) >> 3) & 0x1F)
+#define   C_SQ_CF_WORD1_CF_CONST                                     0xFFFFFF07
+#define   S_SQ_CF_WORD1_COND(x)                                      (((x) & 0x3) << 8)
+#define   G_SQ_CF_WORD1_COND(x)                                      (((x) >> 8) & 0x3)
+#define   C_SQ_CF_WORD1_COND                                         0xFFFFFCFF
+#define   S_SQ_CF_WORD1_COUNT(x)                                     (((x) & 0x3f) << 10)
+#define   G_SQ_CF_WORD1_COUNT(x)                                     (((x) >> 10) & 0x3f)
+#define   C_SQ_CF_WORD1_COUNT                                        0xFFFF03FF
+#define   S_SQ_CF_WORD1_VALID_PIXEL_MODE(x)                          (((x) & 0x1) << 20)
+#define   G_SQ_CF_WORD1_VALID_PIXEL_MODE(x)                          (((x) >> 20) & 0x1)
+#define   C_SQ_CF_WORD1_VALID_PIXEL_MODE                             0xFFEFFFFF
+#define   S_SQ_CF_WORD1_END_OF_PROGRAM(x)                            (((x) & 0x1) << 21)
+#define   G_SQ_CF_WORD1_END_OF_PROGRAM(x)                            (((x) >> 21) & 0x1)
+#define   C_SQ_CF_WORD1_END_OF_PROGRAM                               0xFFDFFFFF
+
+#define   S_SQ_CF_WORD1_CF_INST(x)                                   (((x) & 0xFF) << 22)
+#define   G_SQ_CF_WORD1_CF_INST(x)                                   (((x) >> 22) & 0xFF)
+#define   C_SQ_CF_WORD1_CF_INST                                      0xC03FFFFF
+
+#define   S_SQ_CF_WORD1_WHOLE_QUAD_MODE(x)                           (((x) & 0x1) << 30)
+#define   G_SQ_CF_WORD1_WHOLE_QUAD_MODE(x)                           (((x) >> 30) & 0x1)
+#define   C_SQ_CF_WORD1_WHOLE_QUAD_MODE                              0xBFFFFFFF
+#define   S_SQ_CF_WORD1_BARRIER(x)                                   (((x) & 0x1) << 31)
+#define   G_SQ_CF_WORD1_BARRIER(x)                                   (((x) >> 31) & 0x1)
+#define   C_SQ_CF_WORD1_BARRIER                                      0x7FFFFFFF
+
+/* done */
+#define P_SQ_CF_ALU_WORD0
+#define   S_SQ_CF_ALU_WORD0_ADDR(x)                                  (((x) & 0x3FFFFF) << 0)
+#define   G_SQ_CF_ALU_WORD0_ADDR(x)                                  (((x) >> 0) & 0x3FFFFF)
+#define   C_SQ_CF_ALU_WORD0_ADDR                                     0xFFC00000
+#define   S_SQ_CF_ALU_WORD0_KCACHE_BANK0(x)                          (((x) & 0xF) << 22)
+#define   G_SQ_CF_ALU_WORD0_KCACHE_BANK0(x)                          (((x) >> 22) & 0xF)
+#define   C_SQ_CF_ALU_WORD0_KCACHE_BANK0                             0xFC3FFFFF
+#define   S_SQ_CF_ALU_WORD0_KCACHE_BANK1(x)                          (((x) & 0xF) << 26)
+#define   G_SQ_CF_ALU_WORD0_KCACHE_BANK1(x)                          (((x) >> 26) & 0xF)
+#define   C_SQ_CF_ALU_WORD0_KCACHE_BANK1                             0xC3FFFFFF
+#define   S_SQ_CF_ALU_WORD0_KCACHE_MODE0(x)                          (((x) & 0x3) << 30)
+#define   G_SQ_CF_ALU_WORD0_KCACHE_MODE0(x)                          (((x) >> 30) & 0x3)
+#define   C_SQ_CF_ALU_WORD0_KCACHE_MODE0                             0x3FFFFFFF
+#define P_SQ_CF_ALU_WORD1
+#define   S_SQ_CF_ALU_WORD1_KCACHE_MODE1(x)                          (((x) & 0x3) << 0)
+#define   G_SQ_CF_ALU_WORD1_KCACHE_MODE1(x)                          (((x) >> 0) & 0x3)
+#define   C_SQ_CF_ALU_WORD1_KCACHE_MODE1                             0xFFFFFFFC
+#define   S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x)                          (((x) & 0xFF) << 2)
+#define   G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x)                          (((x) >> 2) & 0xFF)
+#define   C_SQ_CF_ALU_WORD1_KCACHE_ADDR0                             0xFFFFFC03
+#define   S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x)                          (((x) & 0xFF) << 10)
+#define   G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x)                          (((x) >> 10) & 0xFF)
+#define   C_SQ_CF_ALU_WORD1_KCACHE_ADDR1                             0xFFFC03FF
+#define   S_SQ_CF_ALU_WORD1_COUNT(x)                                 (((x) & 0x7F) << 18)
+#define   G_SQ_CF_ALU_WORD1_COUNT(x)                                 (((x) >> 18) & 0x7F)
+#define   C_SQ_CF_ALU_WORD1_COUNT                                    0xFE03FFFF
+#define   S_SQ_CF_ALU_WORD1_ALT_CONST(x)                             (((x) & 0x1) << 25)
+#define   G_SQ_CF_ALU_WORD1_ALT_CONST(x)                             (((x) >> 25) & 0x1)
+#define   C_SQ_CF_ALU_WORD1_ALT_CONST                                0xFDFFFFFF
+#define   S_SQ_CF_ALU_WORD1_CF_INST(x)                               (((x) & 0xF) << 26)
+#define   G_SQ_CF_ALU_WORD1_CF_INST(x)                               (((x) >> 26) & 0xF)
+#define   C_SQ_CF_ALU_WORD1_CF_INST                                  0xC3FFFFFF
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU                         0x00000008
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE             0x00000009
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER               0x0000000A
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER              0x0000000B
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_EXTENDED                    0x0000000C
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE                0x0000000D
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK                   0x0000000E
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER              0x0000000F
+#define   S_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x)                       (((x) & 0x1) << 30)
+#define   G_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x)                       (((x) >> 30) & 0x1)
+#define   C_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE                          0xBFFFFFFF
+#define   S_SQ_CF_ALU_WORD1_BARRIER(x)                               (((x) & 0x1) << 31)
+#define   G_SQ_CF_ALU_WORD1_BARRIER(x)                               (((x) >> 31) & 0x1)
+#define   C_SQ_CF_ALU_WORD1_BARRIER                                  0x7FFFFFFF
+/* extended TODO */
+/* done */
+#define P_SQ_CF_ALLOC_EXPORT_WORD0
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x)                   (((x) & 0x1FFF) << 0)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x)                   (((x) >> 0) & 0x1FFF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE                      0xFFFFE000
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x)                         (((x) & 0x3) << 13)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x)                         (((x) >> 13) & 0x3)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_TYPE                            0xFFFF9FFF
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL               0x00000000
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS                 0x00000001
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM               0x00000002
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK       0x00000003
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x)                       (((x) & 0x7F) << 15)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x)                       (((x) >> 15) & 0x7F)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR                          0xFFC07FFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x)                       (((x) & 0x1) << 22)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x)                       (((x) >> 22) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL                          0xFFBFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x)                    (((x) & 0x7F) << 23)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x)                    (((x) >> 23) & 0x7F)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR                       0xC07FFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x)                    (((x) & 0x3) << 30)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x)                    (((x) >> 30) & 0x3)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE                       0x3FFFFFFF
+/* done */
+#define P_SQ_CF_ALLOC_EXPORT_WORD1
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x)                  (((x) & 0xF) << 16)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x)                  (((x) >> 16) & 0xF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT                     0xFFF0FFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x)             (((x) & 0x1) << 20)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x)             (((x) >> 20) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE                0xFFEFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x)               (((x) & 0x1) << 21)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x)               (((x) >> 21) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM                  0xFFDFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) & 0xFF) << 22)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) >> 22) & 0xFF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST                         0xC03FFFFF
+
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_MARK(x)                         (((x) & 0x1) << 30)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_MARK(x)                         (((x) >> 30) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE                 0xBFFFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x)                      (((x) & 0x1) << 31)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x)                      (((x) >> 31) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER                         0x7FFFFFFF
+
+/* done */
+#define P_SQ_CF_ALLOC_EXPORT_WORD1_BUF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x)               (((x) & 0xFFF) << 0)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x)               (((x) >> 0) & 0xFFF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE                  0xFFFFF000
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x)                (((x) & 0xF) << 12)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x)                (((x) >> 12) & 0xF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK                   0xFFFF0FFF
+#define P_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x)                   (((x) & 0x7) << 0)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x)                   (((x) >> 0) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X                      0xFFFFFFF8
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x)                   (((x) & 0x7) << 3)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x)                   (((x) >> 3) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y                      0xFFFFFFC7
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x)                   (((x) & 0x7) << 6)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x)                   (((x) >> 6) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z                      0xFFFFFE3F
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x)                   (((x) & 0x7) << 9)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x)                   (((x) >> 9) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W                      0xFFFFF1FF
+
+/* done */
+#define P_SQ_ALU_WORD0
+#define   S_SQ_ALU_WORD0_SRC0_SEL(x)                                 (((x) & 0x1FF) << 0)
+#define   G_SQ_ALU_WORD0_SRC0_SEL(x)                                 (((x) >> 0) & 0x1FF)
+#define   C_SQ_ALU_WORD0_SRC0_SEL                                    0xFFFFFE00
+
+/*
+ * 244  ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
+ * 245  ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
+ * 246  ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
+ * 247  ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
+ * 248  SQ_ALU_SRC_0: special constant 0.0.
+ * 249  SQ_ALU_SRC_1: special constant 1.0 float.
+ * 250  SQ_ALU_SRC_1_INT: special constant 1 integer.
+ * 251  SQ_ALU_SRC_M_1_INT: special constant -1 integer.
+ * 252  SQ_ALU_SRC_0_5: special constant 0.5 float.
+ * 253  SQ_ALU_SRC_LITERAL: literal constant.
+ * 254  SQ_ALU_SRC_PV: previous vector result.
+ * 255  SQ_ALU_SRC_PS: previous scalar result.
+ */
+#define     V_SQ_ALU_SRC_0                                           0x000000F8
+#define     V_SQ_ALU_SRC_1                                           0x000000F9
+#define     V_SQ_ALU_SRC_1_INT                                       0x000000FA
+#define     V_SQ_ALU_SRC_M_1_INT                                     0x000000FB
+#define     V_SQ_ALU_SRC_0_5                                         0x000000FC
+#define     V_SQ_ALU_SRC_LITERAL                                     0x000000FD
+#define   S_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) & 0x1) << 9)
+#define   G_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) >> 9) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC0_REL                                    0xFFFFFDFF
+#define   S_SQ_ALU_WORD0_SRC0_CHAN(x)                                (((x) & 0x3) << 10)
+#define   G_SQ_ALU_WORD0_SRC0_CHAN(x)                                (((x) >> 10) & 0x3)
+#define   C_SQ_ALU_WORD0_SRC0_CHAN                                   0xFFFFF3FF
+#define   S_SQ_ALU_WORD0_SRC0_NEG(x)                                 (((x) & 0x1) << 12)
+#define   G_SQ_ALU_WORD0_SRC0_NEG(x)                                 (((x) >> 12) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC0_NEG                                    0xFFFFEFFF
+#define   S_SQ_ALU_WORD0_SRC1_SEL(x)                                 (((x) & 0x1FF) << 13)
+#define   G_SQ_ALU_WORD0_SRC1_SEL(x)                                 (((x) >> 13) & 0x1FF)
+#define   C_SQ_ALU_WORD0_SRC1_SEL                                    0xFFC01FFF
+#define   S_SQ_ALU_WORD0_SRC1_REL(x)                                 (((x) & 0x1) << 22)
+#define   G_SQ_ALU_WORD0_SRC1_REL(x)                                 (((x) >> 22) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC1_REL                                    0xFFBFFFFF
+#define   S_SQ_ALU_WORD0_SRC1_CHAN(x)                                (((x) & 0x3) << 23)
+#define   G_SQ_ALU_WORD0_SRC1_CHAN(x)                                (((x) >> 23) & 0x3)
+#define   C_SQ_ALU_WORD0_SRC1_CHAN                                   0xFE7FFFFF
+#define   S_SQ_ALU_WORD0_SRC1_NEG(x)                                 (((x) & 0x1) << 25)
+#define   G_SQ_ALU_WORD0_SRC1_NEG(x)                                 (((x) >> 25) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC1_NEG                                    0xFDFFFFFF
+#define   S_SQ_ALU_WORD0_INDEX_MODE(x)                               (((x) & 0x7) << 26)
+#define   G_SQ_ALU_WORD0_INDEX_MODE(x)                               (((x) >> 26) & 0x7)
+#define   C_SQ_ALU_WORD0_INDEX_MODE                                  0xE3FFFFFF
+#define   S_SQ_ALU_WORD0_PRED_SEL(x)                                 (((x) & 0x3) << 29)
+#define   G_SQ_ALU_WORD0_PRED_SEL(x)                                 (((x) >> 29) & 0x3)
+#define   C_SQ_ALU_WORD0_PRED_SEL                                    0x9FFFFFFF
+#define   S_SQ_ALU_WORD0_LAST(x)                                     (((x) & 0x1) << 31)
+#define   G_SQ_ALU_WORD0_LAST(x)                                     (((x) >> 31) & 0x1)
+#define   C_SQ_ALU_WORD0_LAST                                        0x7FFFFFFF
+/* same */
+#define P_SQ_ALU_WORD1
+#define   S_SQ_ALU_WORD1_ENCODING(x)                                 (((x) & 0x7) << 15)
+#define   G_SQ_ALU_WORD1_ENCODING(x)                                 (((x) >> 15) & 0x7)
+#define   C_SQ_ALU_WORD1_ENCODING                                    0xFFFC7FFF
+#define   S_SQ_ALU_WORD1_BANK_SWIZZLE(x)                             (((x) & 0x7) << 18)
+#define   G_SQ_ALU_WORD1_BANK_SWIZZLE(x)                             (((x) >> 18) & 0x7)
+#define   C_SQ_ALU_WORD1_BANK_SWIZZLE                                0xFFE3FFFF
+#define   S_SQ_ALU_WORD1_DST_GPR(x)                                  (((x) & 0x7F) << 21)
+#define   G_SQ_ALU_WORD1_DST_GPR(x)                                  (((x) >> 21) & 0x7F)
+#define   C_SQ_ALU_WORD1_DST_GPR                                     0xF01FFFFF
+#define   S_SQ_ALU_WORD1_DST_REL(x)                                  (((x) & 0x1) << 28)
+#define   G_SQ_ALU_WORD1_DST_REL(x)                                  (((x) >> 28) & 0x1)
+#define   C_SQ_ALU_WORD1_DST_REL                                     0xEFFFFFFF
+#define   S_SQ_ALU_WORD1_DST_CHAN(x)                                 (((x) & 0x3) << 29)
+#define   G_SQ_ALU_WORD1_DST_CHAN(x)                                 (((x) >> 29) & 0x3)
+#define   C_SQ_ALU_WORD1_DST_CHAN                                    0x9FFFFFFF
+#define   S_SQ_ALU_WORD1_CLAMP(x)                                    (((x) & 0x1) << 31)
+#define   G_SQ_ALU_WORD1_CLAMP(x)                                    (((x) >> 31) & 0x1)
+#define   C_SQ_ALU_WORD1_CLAMP                                       0x7FFFFFFF
+/* same except maybe encoding */
+#define P_SQ_ALU_WORD1_OP2
+#define   S_SQ_ALU_WORD1_OP2_SRC0_ABS(x)                             (((x) & 0x1) << 0)
+#define   G_SQ_ALU_WORD1_OP2_SRC0_ABS(x)                             (((x) >> 0) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_SRC0_ABS                                0xFFFFFFFE
+#define   S_SQ_ALU_WORD1_OP2_SRC1_ABS(x)                             (((x) & 0x1) << 1)
+#define   G_SQ_ALU_WORD1_OP2_SRC1_ABS(x)                             (((x) >> 1) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_SRC1_ABS                                0xFFFFFFFD
+#define   S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x)                  (((x) & 0x1) << 2)
+#define   G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x)                  (((x) >> 2) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK                     0xFFFFFFFB
+#define   S_SQ_ALU_WORD1_OP2_UPDATE_PRED(x)                          (((x) & 0x1) << 3)
+#define   G_SQ_ALU_WORD1_OP2_UPDATE_PRED(x)                          (((x) >> 3) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_UPDATE_PRED                             0xFFFFFFF7
+#define   S_SQ_ALU_WORD1_OP2_WRITE_MASK(x)                           (((x) & 0x1) << 4)
+#define   G_SQ_ALU_WORD1_OP2_WRITE_MASK(x)                           (((x) >> 4) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_WRITE_MASK                              0xFFFFFFEF
+#define   S_SQ_ALU_WORD1_OP2_OMOD(x)                                 (((x) & 0x3) << 5)
+#define   G_SQ_ALU_WORD1_OP2_OMOD(x)                                 (((x) >> 5) & 0x3)
+#define   C_SQ_ALU_WORD1_OP2_OMOD                                    0xFFFFFF9F
+#define   S_SQ_ALU_WORD1_OP2_ALU_INST(x)                             (((x) & 0x7FF) << 7)
+#define   G_SQ_ALU_WORD1_OP2_ALU_INST(x)                             (((x) >> 7) & 0x7FF)
+#define   C_SQ_ALU_WORD1_OP2_ALU_INST                                0xFFFC007F
+
+#define P_SQ_ALU_WORD1_OP3
+#define   S_SQ_ALU_WORD1_OP3_SRC2_SEL(x)                             (((x) & 0x1FF) << 0)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_SEL(x)                             (((x) >> 0) & 0x1FF)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_SEL                                0xFFFFFE00
+#define   S_SQ_ALU_WORD1_OP3_SRC2_REL(x)                             (((x) & 0x1) << 9)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_REL(x)                             (((x) >> 9) & 0x1)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_REL                                0xFFFFFDFF
+#define   S_SQ_ALU_WORD1_OP3_SRC2_CHAN(x)                            (((x) & 0x3) << 10)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_CHAN(x)                            (((x) >> 10) & 0x3)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_CHAN                               0xFFFFF3FF
+#define   S_SQ_ALU_WORD1_OP3_SRC2_NEG(x)                             (((x) & 0x1) << 12)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_NEG(x)                             (((x) >> 12) & 0x1)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_NEG                                0xFFFFEFFF
+#define   S_SQ_ALU_WORD1_OP3_ALU_INST(x)                             (((x) & 0x1F) << 13)
+#define   G_SQ_ALU_WORD1_OP3_ALU_INST(x)                             (((x) >> 13) & 0x1F)
+#define   C_SQ_ALU_WORD1_OP3_ALU_INST                                0xFFFC1FFF
+/* TODO ADD OTHER OP3 */
+/* done */
+#define P_SQ_VTX_WORD0
+#define   S_SQ_VTX_WORD0_VTX_INST(x)                                 (((x) & 0x1F) << 0)
+#define   G_SQ_VTX_WORD0_VTX_INST(x)                                 (((x) >> 0) & 0x1F)
+#define   C_SQ_VTX_WORD0_VTX_INST                                    0xFFFFFFE0
+#define   S_SQ_VTX_WORD0_FETCH_TYPE(x)                               (((x) & 0x3) << 5)
+#define   G_SQ_VTX_WORD0_FETCH_TYPE(x)                               (((x) >> 5) & 0x3)
+#define   C_SQ_VTX_WORD0_FETCH_TYPE                                  0xFFFFFF9F
+#define   S_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) & 0x1) << 7)
+#define   G_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) >> 7) & 0x1)
+#define   C_SQ_VTX_WORD0_FETCH_WHOLE_QUAD                            0xFFFFFF7F
+#define   S_SQ_VTX_WORD0_BUFFER_ID(x)                                (((x) & 0xFF) << 8)
+#define   G_SQ_VTX_WORD0_BUFFER_ID(x)                                (((x) >> 8) & 0xFF)
+#define   C_SQ_VTX_WORD0_BUFFER_ID                                   0xFFFF00FF
+#define   S_SQ_VTX_WORD0_SRC_GPR(x)                                  (((x) & 0x7F) << 16)
+#define   G_SQ_VTX_WORD0_SRC_GPR(x)                                  (((x) >> 16) & 0x7F)
+#define   C_SQ_VTX_WORD0_SRC_GPR                                     0xFF80FFFF
+#define   S_SQ_VTX_WORD0_SRC_REL(x)                                  (((x) & 0x1) << 23)
+#define   G_SQ_VTX_WORD0_SRC_REL(x)                                  (((x) >> 23) & 0x1)
+#define   C_SQ_VTX_WORD0_SRC_REL                                     0xFF7FFFFF
+#define   S_SQ_VTX_WORD0_SRC_SEL_X(x)                                (((x) & 0x3) << 24)
+#define   G_SQ_VTX_WORD0_SRC_SEL_X(x)                                (((x) >> 24) & 0x3)
+#define   C_SQ_VTX_WORD0_SRC_SEL_X                                   0xFCFFFFFF
+#define   S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x)                         (((x) & 0x3F) << 26)
+#define   G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x)                         (((x) >> 26) & 0x3F)
+#define   C_SQ_VTX_WORD0_MEGA_FETCH_COUNT                            0x03FFFFFF
+/* same WORD 0 */
+#define P_SQ_VTX_WORD1
+#define   S_SQ_VTX_WORD1_DST_SEL_X(x)                                (((x) & 0x7) << 9)
+#define   G_SQ_VTX_WORD1_DST_SEL_X(x)                                (((x) >> 9) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_X                                   0xFFFFF1FF
+#define   S_SQ_VTX_WORD1_DST_SEL_Y(x)                                (((x) & 0x7) << 12)
+#define   G_SQ_VTX_WORD1_DST_SEL_Y(x)                                (((x) >> 12) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_Y                                   0xFFFF8FFF
+#define   S_SQ_VTX_WORD1_DST_SEL_Z(x)                                (((x) & 0x7) << 15)
+#define   G_SQ_VTX_WORD1_DST_SEL_Z(x)                                (((x) >> 15) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_Z                                   0xFFFC7FFF
+#define   S_SQ_VTX_WORD1_DST_SEL_W(x)                                (((x) & 0x7) << 18)
+#define   G_SQ_VTX_WORD1_DST_SEL_W(x)                                (((x) >> 18) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_W                                   0xFFE3FFFF
+#define   S_SQ_VTX_WORD1_USE_CONST_FIELDS(x)                         (((x) & 0x1) << 21)
+#define   G_SQ_VTX_WORD1_USE_CONST_FIELDS(x)                         (((x) >> 21) & 0x1)
+#define   C_SQ_VTX_WORD1_USE_CONST_FIELDS                            0xFFDFFFFF
+#define   S_SQ_VTX_WORD1_DATA_FORMAT(x)                              (((x) & 0x3F) << 22)
+#define   G_SQ_VTX_WORD1_DATA_FORMAT(x)                              (((x) >> 22) & 0x3F)
+#define   C_SQ_VTX_WORD1_DATA_FORMAT                                 0xF03FFFFF
+#define   S_SQ_VTX_WORD1_NUM_FORMAT_ALL(x)                           (((x) & 0x3) << 28)
+#define   G_SQ_VTX_WORD1_NUM_FORMAT_ALL(x)                           (((x) >> 28) & 0x3)
+#define   C_SQ_VTX_WORD1_NUM_FORMAT_ALL                              0xCFFFFFFF
+#define   S_SQ_VTX_WORD1_FORMAT_COMP_ALL(x)                          (((x) & 0x1) << 30)
+#define   G_SQ_VTX_WORD1_FORMAT_COMP_ALL(x)                          (((x) >> 30) & 0x1)
+#define   C_SQ_VTX_WORD1_FORMAT_COMP_ALL                             0xBFFFFFFF
+#define   S_SQ_VTX_WORD1_SRF_MODE_ALL(x)                             (((x) & 0x1) << 31)
+#define   G_SQ_VTX_WORD1_SRF_MODE_ALL(x)                             (((x) >> 31) & 0x1)
+#define   C_SQ_VTX_WORD1_SRF_MODE_ALL                                0x7FFFFFFF
+/* same WORD1 generic */
+#define P_SQ_VTX_WORD1_GPR
+#define   S_SQ_VTX_WORD1_GPR_DST_GPR(x)                              (((x) & 0x7F) << 0)
+#define   G_SQ_VTX_WORD1_GPR_DST_GPR(x)                              (((x) >> 0) & 0x7F)
+#define   C_SQ_VTX_WORD1_GPR_DST_GPR                                 0xFFFFFF80
+#define   S_SQ_VTX_WORD1_GPR_DST_REL(x)                              (((x) & 0x1) << 7)
+#define   G_SQ_VTX_WORD1_GPR_DST_REL(x)                              (((x) >> 7) & 0x1)
+#define   C_SQ_VTX_WORD1_GPR_DST_REL                                 0xFFFFFF7F
+#define P_SQ_VTX_WORD1_SEM
+#define   S_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x)                          (((x) & 0xFF) << 0)
+#define   G_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x)                          (((x) >> 0) & 0xFF)
+#define   C_SQ_VTX_WORD1_SEM_SEMANTIC_ID                             0xFFFFFF00
+#define P_SQ_VTX_WORD2
+#define   S_SQ_VTX_WORD2_OFFSET(x)                                   (((x) & 0xFFFF) << 0)
+#define   G_SQ_VTX_WORD2_OFFSET(x)                                   (((x) >> 0) & 0xFFFF)
+#define   C_SQ_VTX_WORD2_OFFSET                                      0xFFFF0000
+#define   S_SQ_VTX_WORD2_ENDIAN_SWAP(x)                              (((x) & 0x3) << 16)
+#define   G_SQ_VTX_WORD2_ENDIAN_SWAP(x)                              (((x) >> 16) & 0x3)
+#define   C_SQ_VTX_WORD2_ENDIAN_SWAP                                 0xFFFCFFFF
+#define   S_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x)                      (((x) & 0x1) << 18)
+#define   G_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x)                      (((x) >> 18) & 0x1)
+#define   C_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE                         0xFFFBFFFF
+#define   S_SQ_VTX_WORD2_MEGA_FETCH(x)                               (((x) & 0x1) << 19)
+#define   G_SQ_VTX_WORD2_MEGA_FETCH(x)                               (((x) >> 19) & 0x1)
+#define   C_SQ_VTX_WORD2_MEGA_FETCH                                  0xFFF7FFFF
+#define   S_SQ_VTX_WORD2_ALT_CONST(x)                                (((x) & 0x1) << 20)
+#define   G_SQ_VTX_WORD2_ALT_CONST(x)                                (((x) >> 20) & 0x1)
+#define   C_SQ_VTX_WORD2_ALT_CONST                                   0xFFEFFFFF
+#define   S_SQ_VTX_WORD2_BIM(x)                                      (((x) & 0x3) << 21)
+#define   G_SQ_VTX_WORD2_BIM(x)                                      (((x) >> 21) & 0x3)
+#define   C_SQ_VTX_WORD2_BIM                                         0xFF9FFFFF
+/* done */
+
+#define P_SQ_TEX_WORD0
+#define   S_SQ_TEX_WORD0_TEX_INST(x)                                 (((x) & 0x1F) << 0)
+#define   G_SQ_TEX_WORD0_TEX_INST(x)                                 (((x) >> 0) & 0x1F)
+#define   C_SQ_TEX_WORD0_TEX_INST                                    0xFFFFFFE0
+#define   S_SQ_TEX_WORD0_INST_MOD(x)                                 (((x) & 0x3) << 5)
+#define   G_SQ_TEX_WORD0_INST_MOD(x)                                 (((x) >> 5) & 0x3)
+#define   C_SQ_TEX_WORD0_INST_MOD                                    0xFFFFFF9F
+#define   S_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) & 0x1) << 7)
+#define   G_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) >> 7) & 0x1)
+#define   C_SQ_TEX_WORD0_FETCH_WHOLE_QUAD                            0xFFFFFF7F
+#define   S_SQ_TEX_WORD0_RESOURCE_ID(x)                              (((x) & 0xFF) << 8)
+#define   G_SQ_TEX_WORD0_RESOURCE_ID(x)                              (((x) >> 8) & 0xFF)
+#define   C_SQ_TEX_WORD0_RESOURCE_ID                                 0xFFFF00FF
+#define   S_SQ_TEX_WORD0_SRC_GPR(x)                                  (((x) & 0x7F) << 16)
+#define   G_SQ_TEX_WORD0_SRC_GPR(x)                                  (((x) >> 16) & 0x7F)
+#define   C_SQ_TEX_WORD0_SRC_GPR                                     0xFF80FFFF
+#define   S_SQ_TEX_WORD0_SRC_REL(x)                                  (((x) & 0x1) << 23)
+#define   G_SQ_TEX_WORD0_SRC_REL(x)                                  (((x) >> 23) & 0x1)
+#define   C_SQ_TEX_WORD0_SRC_REL                                     0xFF7FFFFF
+#define   S_SQ_TEX_WORD0_ALT_CONST(x)                                (((x) & 0x1) << 24)
+#define   G_SQ_TEX_WORD0_ALT_CONST(x)                                (((x) >> 24) & 0x1)
+#define   C_SQ_TEX_WORD0_ALT_CONST                                   0xFEFFFFFF
+#define   S_SQ_TEX_WORD0_RIM(x)                                      (((x) & 0x3) << 25)
+#define   G_SQ_TEX_WORD0_RIM(x)                                      (((x) >> 25) & 0x3)
+#define   C_SQ_TEX_WORD0_RIM                                         0xF9FFFFFF
+#define   S_SQ_TEX_WORD0_SIM(x)                                      (((x) & 0x3) << 27)
+#define   G_SQ_TEX_WORD0_SIM(x)                                      (((x) >> 27) & 0x3)
+#define   C_SQ_TEX_WORD0_SIM                                         0xE7FFFFFF
+#define P_SQ_TEX_WORD1
+#define   S_SQ_TEX_WORD1_DST_GPR(x)                                  (((x) & 0x7F) << 0)
+#define   G_SQ_TEX_WORD1_DST_GPR(x)                                  (((x) >> 0) & 0x7F)
+#define   C_SQ_TEX_WORD1_DST_GPR                                     0xFFFFFF80
+#define   S_SQ_TEX_WORD1_DST_REL(x)                                  (((x) & 0x1) << 7)
+#define   G_SQ_TEX_WORD1_DST_REL(x)                                  (((x) >> 7) & 0x1)
+#define   C_SQ_TEX_WORD1_DST_REL                                     0xFFFFFF7F
+#define   S_SQ_TEX_WORD1_DST_SEL_X(x)                                (((x) & 0x7) << 9)
+#define   G_SQ_TEX_WORD1_DST_SEL_X(x)                                (((x) >> 9) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_X                                   0xFFFFF1FF
+#define   S_SQ_TEX_WORD1_DST_SEL_Y(x)                                (((x) & 0x7) << 12)
+#define   G_SQ_TEX_WORD1_DST_SEL_Y(x)                                (((x) >> 12) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_Y                                   0xFFFF8FFF
+#define   S_SQ_TEX_WORD1_DST_SEL_Z(x)                                (((x) & 0x7) << 15)
+#define   G_SQ_TEX_WORD1_DST_SEL_Z(x)                                (((x) >> 15) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_Z                                   0xFFFC7FFF
+#define   S_SQ_TEX_WORD1_DST_SEL_W(x)                                (((x) & 0x7) << 18)
+#define   G_SQ_TEX_WORD1_DST_SEL_W(x)                                (((x) >> 18) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_W                                   0xFFE3FFFF
+#define   S_SQ_TEX_WORD1_LOD_BIAS(x)                                 (((x) & 0x7F) << 21)
+#define   G_SQ_TEX_WORD1_LOD_BIAS(x)                                 (((x) >> 21) & 0x7F)
+#define   C_SQ_TEX_WORD1_LOD_BIAS                                    0xF01FFFFF
+#define   S_SQ_TEX_WORD1_COORD_TYPE_X(x)                             (((x) & 0x1) << 28)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_X(x)                             (((x) >> 28) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_X                                0xEFFFFFFF
+#define     V_SQ_TEX_WORD1_COORD_UNNORMALIZED                        0x00000000
+#define     V_SQ_TEX_WORD1_COORD_NORMALIZED                          0x00000001
+#define   S_SQ_TEX_WORD1_COORD_TYPE_Y(x)                             (((x) & 0x1) << 29)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_Y(x)                             (((x) >> 29) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_Y                                0xDFFFFFFF
+#define   S_SQ_TEX_WORD1_COORD_TYPE_Z(x)                             (((x) & 0x1) << 30)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_Z(x)                             (((x) >> 30) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_Z                                0xBFFFFFFF
+#define   S_SQ_TEX_WORD1_COORD_TYPE_W(x)                             (((x) & 0x1) << 31)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_W(x)                             (((x) >> 31) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_W                                0x7FFFFFFF
+#define P_SQ_TEX_WORD2
+#define   S_SQ_TEX_WORD2_OFFSET_X(x)                                 (((x) & 0x1F) << 0)
+#define   G_SQ_TEX_WORD2_OFFSET_X(x)                                 (((x) >> 0) & 0x1F)
+#define   C_SQ_TEX_WORD2_OFFSET_X                                    0xFFFFFFE0
+#define   S_SQ_TEX_WORD2_OFFSET_Y(x)                                 (((x) & 0x1F) << 5)
+#define   G_SQ_TEX_WORD2_OFFSET_Y(x)                                 (((x) >> 5) & 0x1F)
+#define   C_SQ_TEX_WORD2_OFFSET_Y                                    0xFFFFFC1F
+#define   S_SQ_TEX_WORD2_OFFSET_Z(x)                                 (((x) & 0x1F) << 10)
+#define   G_SQ_TEX_WORD2_OFFSET_Z(x)                                 (((x) >> 10) & 0x1F)
+#define   C_SQ_TEX_WORD2_OFFSET_Z                                    0xFFFF83FF
+#define   S_SQ_TEX_WORD2_SAMPLER_ID(x)                               (((x) & 0x1F) << 15)
+#define   G_SQ_TEX_WORD2_SAMPLER_ID(x)                               (((x) >> 15) & 0x1F)
+#define   C_SQ_TEX_WORD2_SAMPLER_ID                                  0xFFF07FFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_X(x)                                (((x) & 0x7) << 20)
+#define   G_SQ_TEX_WORD2_SRC_SEL_X(x)                                (((x) >> 20) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_X                                   0xFF8FFFFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_Y(x)                                (((x) & 0x7) << 23)
+#define   G_SQ_TEX_WORD2_SRC_SEL_Y(x)                                (((x) >> 23) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_Y                                   0xFC7FFFFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_Z(x)                                (((x) & 0x7) << 26)
+#define   G_SQ_TEX_WORD2_SRC_SEL_Z(x)                                (((x) >> 26) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_Z                                   0xE3FFFFFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) & 0x7) << 29)
+#define   G_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) >> 29) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
+
+#define V_SQ_CF_COND_ACTIVE                             0x00
+#define V_SQ_CF_COND_FALSE                              0x01
+#define V_SQ_CF_COND_BOOL                               0x02
+#define V_SQ_CF_COND_NOT_BOOL                           0x03
+
+#define V_SQ_REL_ABSOLUTE 0
+#define V_SQ_REL_RELATIVE 1
+#endif
diff --git a/src/gallium/drivers/r600/eg_state_inlines.h b/src/gallium/drivers/r600/eg_state_inlines.h
new file mode 100644 (file)
index 0000000..4e35146
--- /dev/null
@@ -0,0 +1,434 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef EG_STATE_INLINES_H
+#define EG_STATE_INLINES_H
+
+#include "util/u_format.h"
+#include "evergreend.h"
+
+static INLINE uint32_t r600_translate_blend_function(int blend_func)
+{
+       switch (blend_func) {
+       case PIPE_BLEND_ADD:
+               return V_028780_COMB_DST_PLUS_SRC;
+       case PIPE_BLEND_SUBTRACT:
+               return V_028780_COMB_SRC_MINUS_DST;
+       case PIPE_BLEND_REVERSE_SUBTRACT:
+               return V_028780_COMB_DST_MINUS_SRC;
+       case PIPE_BLEND_MIN:
+               return V_028780_COMB_MIN_DST_SRC;
+       case PIPE_BLEND_MAX:
+               return V_028780_COMB_MAX_DST_SRC;
+       default:
+               R600_ERR("Unknown blend function %d\n", blend_func);
+               assert(0);
+               break;
+       }
+       return 0;
+}
+
+static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
+{
+       switch (blend_fact) {
+       case PIPE_BLENDFACTOR_ONE:
+               return V_028780_BLEND_ONE;
+       case PIPE_BLENDFACTOR_SRC_COLOR:
+               return V_028780_BLEND_SRC_COLOR;
+       case PIPE_BLENDFACTOR_SRC_ALPHA:
+               return V_028780_BLEND_SRC_ALPHA;
+       case PIPE_BLENDFACTOR_DST_ALPHA:
+               return V_028780_BLEND_DST_ALPHA;
+       case PIPE_BLENDFACTOR_DST_COLOR:
+               return V_028780_BLEND_DST_COLOR;
+       case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+               return V_028780_BLEND_SRC_ALPHA_SATURATE;
+       case PIPE_BLENDFACTOR_CONST_COLOR:
+               return V_028780_BLEND_CONST_COLOR;
+       case PIPE_BLENDFACTOR_CONST_ALPHA:
+               return V_028780_BLEND_CONST_ALPHA;
+       case PIPE_BLENDFACTOR_ZERO:
+               return V_028780_BLEND_ZERO;
+       case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+               return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
+       case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+               return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
+       case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+               return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
+       case PIPE_BLENDFACTOR_INV_DST_COLOR:
+               return V_028780_BLEND_ONE_MINUS_DST_COLOR;
+       case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+               return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
+       case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+               return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
+       case PIPE_BLENDFACTOR_SRC1_COLOR:
+               return V_028780_BLEND_SRC1_COLOR;
+       case PIPE_BLENDFACTOR_SRC1_ALPHA:
+               return V_028780_BLEND_SRC1_ALPHA;
+       case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+               return V_028780_BLEND_INV_SRC1_COLOR;
+       case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+               return V_028780_BLEND_INV_SRC1_ALPHA;
+       default:
+               R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
+               assert(0);
+               break;
+       }
+       return 0;
+}
+
+static INLINE uint32_t r600_translate_stencil_op(int s_op)
+{
+       switch (s_op) {
+       case PIPE_STENCIL_OP_KEEP:
+               return V_028800_STENCIL_KEEP;
+       case PIPE_STENCIL_OP_ZERO:
+               return V_028800_STENCIL_ZERO;
+       case PIPE_STENCIL_OP_REPLACE:
+               return V_028800_STENCIL_REPLACE;
+       case PIPE_STENCIL_OP_INCR:
+               return V_028800_STENCIL_INCR;
+       case PIPE_STENCIL_OP_DECR:
+               return V_028800_STENCIL_DECR;
+       case PIPE_STENCIL_OP_INCR_WRAP:
+               return V_028800_STENCIL_INCR_WRAP;
+       case PIPE_STENCIL_OP_DECR_WRAP:
+               return V_028800_STENCIL_DECR_WRAP;
+       case PIPE_STENCIL_OP_INVERT:
+               return V_028800_STENCIL_INVERT;
+       default:
+               R600_ERR("Unknown stencil op %d", s_op);
+               assert(0);
+               break;
+       }
+       return 0;
+}
+
+/* translates straight */
+static INLINE uint32_t r600_translate_ds_func(int func)
+{
+       return func;
+}
+
+static inline unsigned r600_tex_wrap(unsigned wrap)
+{
+       switch (wrap) {
+       default:
+       case PIPE_TEX_WRAP_REPEAT:
+               return V_03C000_SQ_TEX_WRAP;
+       case PIPE_TEX_WRAP_CLAMP:
+               return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
+       case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+               return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+       case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+               return V_03C000_SQ_TEX_CLAMP_BORDER;
+       case PIPE_TEX_WRAP_MIRROR_REPEAT:
+               return V_03C000_SQ_TEX_MIRROR;
+       case PIPE_TEX_WRAP_MIRROR_CLAMP:
+               return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+       case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+               return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+       case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+               return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
+       }
+}
+
+static inline unsigned r600_tex_filter(unsigned filter)
+{
+       switch (filter) {
+       default:
+       case PIPE_TEX_FILTER_NEAREST:
+               return V_03C000_SQ_TEX_XY_FILTER_POINT;
+       case PIPE_TEX_FILTER_LINEAR:
+               return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
+       }
+}
+
+static inline unsigned r600_tex_mipfilter(unsigned filter)
+{
+       switch (filter) {
+       case PIPE_TEX_MIPFILTER_NEAREST:
+               return V_03C000_SQ_TEX_Z_FILTER_POINT;
+       case PIPE_TEX_MIPFILTER_LINEAR:
+               return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
+       default:
+       case PIPE_TEX_MIPFILTER_NONE:
+               return V_03C000_SQ_TEX_Z_FILTER_NONE;
+       }
+}
+
+static inline unsigned r600_tex_compare(unsigned compare)
+{
+       switch (compare) {
+       default:
+       case PIPE_FUNC_NEVER:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
+       case PIPE_FUNC_LESS:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
+       case PIPE_FUNC_EQUAL:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
+       case PIPE_FUNC_LEQUAL:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+       case PIPE_FUNC_GREATER:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
+       case PIPE_FUNC_NOTEQUAL:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+       case PIPE_FUNC_GEQUAL:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+       case PIPE_FUNC_ALWAYS:
+               return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+       }
+}
+
+static inline unsigned r600_tex_swizzle(unsigned swizzle)
+{
+       switch (swizzle) {
+       case PIPE_SWIZZLE_RED:
+               return V_030010_SQ_SEL_X;
+       case PIPE_SWIZZLE_GREEN:
+               return V_030010_SQ_SEL_Y;
+       case PIPE_SWIZZLE_BLUE:
+               return V_030010_SQ_SEL_Z;
+       case PIPE_SWIZZLE_ALPHA:
+               return V_030010_SQ_SEL_W;
+       case PIPE_SWIZZLE_ZERO:
+               return V_030010_SQ_SEL_0;
+       default:
+       case PIPE_SWIZZLE_ONE:
+               return V_030010_SQ_SEL_1;
+       }
+}
+
+static inline unsigned r600_format_type(unsigned format_type)
+{
+       switch (format_type) {
+       default:
+       case UTIL_FORMAT_TYPE_UNSIGNED:
+               return V_030010_SQ_FORMAT_COMP_UNSIGNED;
+       case UTIL_FORMAT_TYPE_SIGNED:
+               return V_030010_SQ_FORMAT_COMP_SIGNED;
+       case UTIL_FORMAT_TYPE_FIXED:
+               return V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
+       }
+}
+
+static inline unsigned r600_tex_dim(unsigned dim)
+{
+       switch (dim) {
+       default:
+       case PIPE_TEXTURE_1D:
+               return V_030000_SQ_TEX_DIM_1D;
+       case PIPE_TEXTURE_2D:
+       case PIPE_TEXTURE_RECT:
+               return V_030000_SQ_TEX_DIM_2D;
+       case PIPE_TEXTURE_3D:
+               return V_030000_SQ_TEX_DIM_3D;
+       case PIPE_TEXTURE_CUBE:
+               return V_030000_SQ_TEX_DIM_CUBEMAP;
+       }
+}
+
+static inline uint32_t r600_translate_dbformat(enum pipe_format format)
+{
+       switch (format) {
+       case PIPE_FORMAT_Z16_UNORM:
+               return V_028040_Z_16;
+       case PIPE_FORMAT_Z24X8_UNORM:
+               return V_028040_Z_24;
+       case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+               return V_028040_Z_24;
+       default:
+               return ~0;
+       }
+}
+
+static inline uint32_t r600_translate_colorswap(enum pipe_format format)
+{
+       switch (format) {
+               /* 8-bit buffers. */
+       case PIPE_FORMAT_A8_UNORM:
+       case PIPE_FORMAT_I8_UNORM:
+       case PIPE_FORMAT_L8_UNORM:
+       case PIPE_FORMAT_R8_UNORM:
+       case PIPE_FORMAT_R8_SNORM:
+               return V_028C70_SWAP_STD;
+
+               /* 16-bit buffers. */
+       case PIPE_FORMAT_B5G6R5_UNORM:
+               return V_028C70_SWAP_STD_REV;
+
+       case PIPE_FORMAT_B5G5R5A1_UNORM:
+       case PIPE_FORMAT_B5G5R5X1_UNORM:
+               return V_028C70_SWAP_ALT;
+
+       case PIPE_FORMAT_B4G4R4A4_UNORM:
+       case PIPE_FORMAT_B4G4R4X4_UNORM:
+               return V_028C70_SWAP_ALT;
+               /* 32-bit buffers. */
+
+       case PIPE_FORMAT_A8B8G8R8_SRGB:
+               return V_028C70_SWAP_STD_REV;
+       case PIPE_FORMAT_B8G8R8A8_SRGB:
+               return V_028C70_SWAP_ALT;
+
+       case PIPE_FORMAT_B8G8R8A8_UNORM:
+       case PIPE_FORMAT_B8G8R8X8_UNORM:
+               return V_028C70_SWAP_ALT;
+
+       case PIPE_FORMAT_A8R8G8B8_UNORM:
+       case PIPE_FORMAT_X8R8G8B8_UNORM:
+               return V_028C70_SWAP_ALT_REV;
+       case PIPE_FORMAT_R8G8B8A8_SNORM:
+       case PIPE_FORMAT_R8G8B8X8_UNORM:
+               return V_028C70_SWAP_STD;
+
+       case PIPE_FORMAT_A8B8G8R8_UNORM:
+       case PIPE_FORMAT_X8B8G8R8_UNORM:
+               //        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+               return V_028C70_SWAP_STD_REV;
+
+       case PIPE_FORMAT_Z24X8_UNORM:
+       case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+               return V_028C70_SWAP_STD;
+
+       case PIPE_FORMAT_R10G10B10A2_UNORM:
+       case PIPE_FORMAT_R10G10B10X2_SNORM:
+       case PIPE_FORMAT_B10G10R10A2_UNORM:
+       case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+               return V_028C70_SWAP_STD_REV;
+
+               /* 64-bit buffers. */
+       case PIPE_FORMAT_R16G16B16A16_UNORM:
+       case PIPE_FORMAT_R16G16B16A16_SNORM:
+               //              return V_028C70_COLOR_16_16_16_16;
+       case PIPE_FORMAT_R16G16B16A16_FLOAT:
+               //              return V_028C70_COLOR_16_16_16_16_FLOAT;
+
+               /* 128-bit buffers. */
+       case PIPE_FORMAT_R32G32B32A32_FLOAT:
+               //              return V_028C70_COLOR_32_32_32_32_FLOAT;
+               return 0;
+       default:
+               R600_ERR("unsupported colorswap format %d\n", format);
+               return ~0;
+       }
+       return ~0;
+}
+
+static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
+{
+       switch (format) {
+               /* 8-bit buffers. */
+       case PIPE_FORMAT_A8_UNORM:
+       case PIPE_FORMAT_I8_UNORM:
+       case PIPE_FORMAT_L8_UNORM:
+       case PIPE_FORMAT_R8_UNORM:
+       case PIPE_FORMAT_R8_SNORM:
+               return V_028C70_COLOR_8;
+
+               /* 16-bit buffers. */
+       case PIPE_FORMAT_B5G6R5_UNORM:
+               return V_028C70_COLOR_5_6_5;
+
+       case PIPE_FORMAT_B5G5R5A1_UNORM:
+       case PIPE_FORMAT_B5G5R5X1_UNORM:
+               return V_028C70_COLOR_1_5_5_5;
+
+       case PIPE_FORMAT_B4G4R4A4_UNORM:
+       case PIPE_FORMAT_B4G4R4X4_UNORM:
+               return V_028C70_COLOR_4_4_4_4;
+
+               /* 32-bit buffers. */
+       case PIPE_FORMAT_A8B8G8R8_SRGB:
+       case PIPE_FORMAT_A8B8G8R8_UNORM:
+       case PIPE_FORMAT_A8R8G8B8_UNORM:
+       case PIPE_FORMAT_B8G8R8A8_SRGB:
+       case PIPE_FORMAT_B8G8R8A8_UNORM:
+       case PIPE_FORMAT_B8G8R8X8_UNORM:
+       case PIPE_FORMAT_R8G8B8A8_SNORM:
+       case PIPE_FORMAT_R8G8B8A8_UNORM:
+       case PIPE_FORMAT_R8G8B8X8_UNORM:
+       case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+       case PIPE_FORMAT_X8B8G8R8_UNORM:
+       case PIPE_FORMAT_X8R8G8B8_UNORM:
+       case PIPE_FORMAT_R8G8B8_UNORM:
+               return V_028C70_COLOR_8_8_8_8;
+
+       case PIPE_FORMAT_R10G10B10A2_UNORM:
+       case PIPE_FORMAT_R10G10B10X2_SNORM:
+       case PIPE_FORMAT_B10G10R10A2_UNORM:
+       case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+               return V_028C70_COLOR_10_10_10_2;
+
+       case PIPE_FORMAT_Z24X8_UNORM:
+       case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+               return V_028C70_COLOR_8_24;
+
+       case PIPE_FORMAT_R32_FLOAT:
+               return V_028C70_COLOR_32_FLOAT;
+
+               /* 64-bit buffers. */
+       case PIPE_FORMAT_R16G16B16A16_UNORM:
+       case PIPE_FORMAT_R16G16B16A16_SNORM:
+               return V_028C70_COLOR_16_16_16_16;
+       case PIPE_FORMAT_R16G16B16A16_FLOAT:
+               return V_028C70_COLOR_16_16_16_16_FLOAT;
+       case PIPE_FORMAT_R32G32_FLOAT:
+               return V_028C70_COLOR_32_32_FLOAT;
+
+               /* 128-bit buffers. */
+       case PIPE_FORMAT_R32G32B32_FLOAT:
+               return V_028C70_COLOR_32_32_32_FLOAT;
+       case PIPE_FORMAT_R32G32B32A32_FLOAT:
+               return V_028C70_COLOR_32_32_32_32_FLOAT;
+
+               /* YUV buffers. */
+       case PIPE_FORMAT_UYVY:
+       case PIPE_FORMAT_YUYV:
+       default:
+               R600_ERR("unsupported color format %d\n", format);
+               return ~0; /* Unsupported. */
+       }
+}
+
+static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
+{
+       return r600_translate_texformat(format, NULL, NULL, NULL) != ~0;
+}
+
+static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format)
+{
+       return r600_translate_colorformat(format) != ~0 &&
+               r600_translate_colorswap(format) != ~0;
+}
+
+static INLINE boolean r600_is_zs_format_supported(enum pipe_format format)
+{
+       return r600_translate_dbformat(format) != ~0;
+}
+
+static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format)
+{
+       return r600_translate_colorformat(format) != ~0;
+}
+
+#endif
diff --git a/src/gallium/drivers/r600/eg_states_inc.h b/src/gallium/drivers/r600/eg_states_inc.h
new file mode 100644 (file)
index 0000000..ebfc36c
--- /dev/null
@@ -0,0 +1,521 @@
+/* This file is autogenerated from eg_states.h - do not edit directly */
+/* autogenerating script is gen_eg_states.py */
+
+/* EG_CONFIG */
+#define EG_CONFIG__SQ_CONFIG           0
+#define EG_CONFIG__SPI_CONFIG_CNTL             1
+#define EG_CONFIG__SPI_CONFIG_CNTL_1           2
+#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1              3
+#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2              4
+#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3              5
+#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1           6
+#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2           7
+#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1            8
+#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2            9
+#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3            10
+#define EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                11
+#define EG_CONFIG__PA_CL_ENHANCE               12
+#define EG_CONFIG__SQ_DYN_GPR_RESOURCE_LIMIT_1         13
+#define EG_CONFIG__SQ_LDS_ALLOC_PS             14
+#define EG_CONFIG__SX_MISC             15
+#define EG_CONFIG__SQ_ESGS_RING_ITEMSIZE               16
+#define EG_CONFIG__SQ_GSVS_RING_ITEMSIZE               17
+#define EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE              18
+#define EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE              19
+#define EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE              20
+#define EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE              21
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE         22
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1               23
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2               24
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3               25
+#define EG_CONFIG__VGT_OUTPUT_PATH_CNTL                26
+#define EG_CONFIG__VGT_HOS_CNTL                27
+#define EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL              28
+#define EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL              29
+#define EG_CONFIG__VGT_HOS_REUSE_DEPTH         30
+#define EG_CONFIG__VGT_GROUP_PRIM_TYPE         31
+#define EG_CONFIG__VGT_GROUP_FIRST_DECR                32
+#define EG_CONFIG__VGT_GROUP_DECR              33
+#define EG_CONFIG__VGT_GROUP_VECT_0_CNTL               34
+#define EG_CONFIG__VGT_GROUP_VECT_1_CNTL               35
+#define EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL           36
+#define EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL           37
+#define EG_CONFIG__VGT_GS_MODE         38
+#define EG_CONFIG__PA_SC_MODE_CNTL_0           39
+#define EG_CONFIG__PA_SC_MODE_CNTL_1           40
+#define EG_CONFIG__VGT_REUSE_OFF               41
+#define EG_CONFIG__VGT_VTX_CNT_EN              42
+#define EG_CONFIG__VGT_SHADER_STAGES_EN                43
+#define EG_CONFIG__VGT_STRMOUT_CONFIG          44
+#define EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG           45
+#define EG_CONFIG_SIZE         46
+#define EG_CONFIG_PM4 128              
+
+/* EG_CB_CNTL */
+#define EG_CB_CNTL__CB_TARGET_MASK             0
+#define EG_CB_CNTL__CB_SHADER_MASK             1
+#define EG_CB_CNTL__CB_COLOR_CONTROL           2
+#define EG_CB_CNTL__PA_SC_AA_CONFIG            3
+#define EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX          4
+#define EG_CB_CNTL__PA_SC_AA_MASK              5
+#define EG_CB_CNTL_SIZE                6
+#define EG_CB_CNTL_PM4 128             
+
+/* EG_RASTERIZER */
+#define EG_RASTERIZER__SPI_INTERP_CONTROL_0            0
+#define EG_RASTERIZER__PA_CL_CLIP_CNTL         1
+#define EG_RASTERIZER__PA_SU_SC_MODE_CNTL              2
+#define EG_RASTERIZER__PA_CL_VS_OUT_CNTL               3
+#define EG_RASTERIZER__PA_CL_NANINF_CNTL               4
+#define EG_RASTERIZER__PA_SU_POINT_SIZE                5
+#define EG_RASTERIZER__PA_SU_POINT_MINMAX              6
+#define EG_RASTERIZER__PA_SU_LINE_CNTL         7
+#define EG_RASTERIZER__PA_SC_MPASS_PS_CNTL             8
+#define EG_RASTERIZER__PA_SC_LINE_CNTL         9
+#define EG_RASTERIZER__PA_SU_VTX_CNTL          10
+#define EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ          11
+#define EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ          12
+#define EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ          13
+#define EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ          14
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL           15
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP         16
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE           17
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET          18
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE            19
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET           20
+#define EG_RASTERIZER_SIZE             21
+#define EG_RASTERIZER_PM4 128          
+
+/* EG_VIEWPORT */
+#define EG_VIEWPORT__PA_SC_VPORT_ZMIN_0                0
+#define EG_VIEWPORT__PA_SC_VPORT_ZMAX_0                1
+#define EG_VIEWPORT__PA_CL_VPORT_XSCALE_0              2
+#define EG_VIEWPORT__PA_CL_VPORT_YSCALE_0              3
+#define EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0              4
+#define EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0             5
+#define EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0             6
+#define EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0             7
+#define EG_VIEWPORT__PA_CL_VTE_CNTL            8
+#define EG_VIEWPORT_SIZE               9
+#define EG_VIEWPORT_PM4 128            
+
+/* EG_SCISSOR */
+#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL            0
+#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR            1
+#define EG_SCISSOR__PA_SC_WINDOW_OFFSET                2
+#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL            3
+#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR            4
+#define EG_SCISSOR__PA_SC_CLIPRECT_RULE                5
+#define EG_SCISSOR__PA_SC_CLIPRECT_0_TL                6
+#define EG_SCISSOR__PA_SC_CLIPRECT_0_BR                7
+#define EG_SCISSOR__PA_SC_CLIPRECT_1_TL                8
+#define EG_SCISSOR__PA_SC_CLIPRECT_1_BR                9
+#define EG_SCISSOR__PA_SC_CLIPRECT_2_TL                10
+#define EG_SCISSOR__PA_SC_CLIPRECT_2_BR                11
+#define EG_SCISSOR__PA_SC_CLIPRECT_3_TL                12
+#define EG_SCISSOR__PA_SC_CLIPRECT_3_BR                13
+#define EG_SCISSOR__PA_SC_EDGERULE             14
+#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL           15
+#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR           16
+#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL           17
+#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR           18
+#define EG_SCISSOR__PA_SU_HARDWARE_SCREEN_OFFSET               19
+#define EG_SCISSOR_SIZE                20
+#define EG_SCISSOR_PM4 128             
+
+/* EG_BLEND */
+#define EG_BLEND__CB_BLEND_RED         0
+#define EG_BLEND__CB_BLEND_GREEN               1
+#define EG_BLEND__CB_BLEND_BLUE                2
+#define EG_BLEND__CB_BLEND_ALPHA               3
+#define EG_BLEND__CB_BLEND0_CONTROL            4
+#define EG_BLEND__CB_BLEND1_CONTROL            5
+#define EG_BLEND__CB_BLEND2_CONTROL            6
+#define EG_BLEND__CB_BLEND3_CONTROL            7
+#define EG_BLEND__CB_BLEND4_CONTROL            8
+#define EG_BLEND__CB_BLEND5_CONTROL            9
+#define EG_BLEND__CB_BLEND6_CONTROL            10
+#define EG_BLEND__CB_BLEND7_CONTROL            11
+#define EG_BLEND_SIZE          12
+#define EG_BLEND_PM4 128               
+
+/* EG_DSA */
+#define EG_DSA__DB_STENCIL_CLEAR               0
+#define EG_DSA__DB_DEPTH_CLEAR         1
+#define EG_DSA__SX_ALPHA_TEST_CONTROL          2
+#define EG_DSA__DB_STENCILREFMASK              3
+#define EG_DSA__DB_STENCILREFMASK_BF           4
+#define EG_DSA__SX_ALPHA_REF           5
+#define EG_DSA__SPI_FOG_CNTL           6
+#define EG_DSA__DB_DEPTH_CONTROL               7
+#define EG_DSA__DB_SHADER_CONTROL              8
+#define EG_DSA__DB_RENDER_CONTROL              9
+#define EG_DSA__DB_RENDER_OVERRIDE             10
+#define EG_DSA__DB_RENDER_OVERRIDE2            11
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE0             12
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE1             13
+#define EG_DSA__DB_PRELOAD_CONTROL             14
+#define EG_DSA__DB_ALPHA_TO_MASK               15
+#define EG_DSA_SIZE            16
+#define EG_DSA_PM4 128         
+
+/* EG_VS_SHADER */
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_0                0
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_1                1
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_2                2
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_3                3
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_4                4
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_5                5
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_6                6
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_7                7
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_8                8
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_9                9
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_10               10
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_11               11
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_12               12
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_13               13
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_14               14
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_15               15
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_16               16
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_17               17
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_18               18
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_19               19
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_20               20
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_21               21
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_22               22
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_23               23
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_24               24
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_25               25
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_26               26
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_27               27
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_28               28
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_29               29
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_30               30
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_31               31
+#define EG_VS_SHADER__SPI_VS_OUT_ID_0          32
+#define EG_VS_SHADER__SPI_VS_OUT_ID_1          33
+#define EG_VS_SHADER__SPI_VS_OUT_ID_2          34
+#define EG_VS_SHADER__SPI_VS_OUT_ID_3          35
+#define EG_VS_SHADER__SPI_VS_OUT_ID_4          36
+#define EG_VS_SHADER__SPI_VS_OUT_ID_5          37
+#define EG_VS_SHADER__SPI_VS_OUT_ID_6          38
+#define EG_VS_SHADER__SPI_VS_OUT_ID_7          39
+#define EG_VS_SHADER__SPI_VS_OUT_ID_8          40
+#define EG_VS_SHADER__SPI_VS_OUT_ID_9          41
+#define EG_VS_SHADER__SPI_VS_OUT_CONFIG                42
+#define EG_VS_SHADER__SQ_PGM_START_VS          43
+#define EG_VS_SHADER__SQ_PGM_RESOURCES_VS              44
+#define EG_VS_SHADER__SQ_PGM_RESOURCES_2_VS            45
+#define EG_VS_SHADER__SQ_PGM_START_FS          46
+#define EG_VS_SHADER__SQ_PGM_RESOURCES_FS              47
+#define EG_VS_SHADER_SIZE              48
+#define EG_VS_SHADER_PM4 128           
+
+/* EG_PS_SHADER */
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_0              0
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_1              1
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_2              2
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_3              3
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_4              4
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_5              5
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_6              6
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_7              7
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_8              8
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_9              9
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_10             10
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_11             11
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_12             12
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_13             13
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_14             14
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_15             15
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_16             16
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_17             17
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_18             18
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_19             19
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_20             20
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_21             21
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_22             22
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_23             23
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_24             24
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_25             25
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_26             26
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_27             27
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_28             28
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_29             29
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_30             30
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_31             31
+#define EG_PS_SHADER__SPI_THREAD_GROUPING              32
+#define EG_PS_SHADER__SPI_PS_IN_CONTROL_0              33
+#define EG_PS_SHADER__SPI_PS_IN_CONTROL_1              34
+#define EG_PS_SHADER__SPI_INPUT_Z              35
+#define EG_PS_SHADER__SPI_BARYC_CNTL           36
+#define EG_PS_SHADER__SPI_PS_IN_CONTROL_2              37
+#define EG_PS_SHADER__SPI_COMPUTE_INPUT_CNTL           38
+#define EG_PS_SHADER__SQ_PGM_START_PS          39
+#define EG_PS_SHADER__SQ_PGM_RESOURCES_PS              40
+#define EG_PS_SHADER__SQ_PGM_RESOURCES_2_PS            41
+#define EG_PS_SHADER__SQ_PGM_EXPORTS_PS                42
+#define EG_PS_SHADER_SIZE              43
+#define EG_PS_SHADER_PM4 128           
+
+/* EG_UCP */
+#define EG_UCP__PA_CL_UCP0_X           0
+#define EG_UCP__PA_CL_UCP0_Y           1
+#define EG_UCP__PA_CL_UCP0_Z           2
+#define EG_UCP__PA_CL_UCP0_W           3
+#define EG_UCP__PA_CL_UCP1_X           4
+#define EG_UCP__PA_CL_UCP1_Y           5
+#define EG_UCP__PA_CL_UCP1_Z           6
+#define EG_UCP__PA_CL_UCP1_W           7
+#define EG_UCP__PA_CL_UCP2_X           8
+#define EG_UCP__PA_CL_UCP2_Y           9
+#define EG_UCP__PA_CL_UCP2_Z           10
+#define EG_UCP__PA_CL_UCP2_W           11
+#define EG_UCP__PA_CL_UCP3_X           12
+#define EG_UCP__PA_CL_UCP3_Y           13
+#define EG_UCP__PA_CL_UCP3_Z           14
+#define EG_UCP__PA_CL_UCP3_W           15
+#define EG_UCP__PA_CL_UCP4_X           16
+#define EG_UCP__PA_CL_UCP4_Y           17
+#define EG_UCP__PA_CL_UCP4_Z           18
+#define EG_UCP__PA_CL_UCP4_W           19
+#define EG_UCP__PA_CL_UCP5_X           20
+#define EG_UCP__PA_CL_UCP5_Y           21
+#define EG_UCP__PA_CL_UCP5_Z           22
+#define EG_UCP__PA_CL_UCP5_W           23
+#define EG_UCP_SIZE            24
+#define EG_UCP_PM4 128         
+
+/* EG_VS_CBUF */
+#define EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0         0
+#define EG_VS_CBUF__ALU_CONST_CACHE_VS_0               1
+#define EG_VS_CBUF_SIZE                2
+#define EG_VS_CBUF_PM4 128             
+
+/* EG_PS_CBUF */
+#define EG_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0         0
+#define EG_PS_CBUF__ALU_CONST_CACHE_PS_0               1
+#define EG_PS_CBUF_SIZE                2
+#define EG_PS_CBUF_PM4 128             
+
+/* EG_PS_RESOURCE */
+#define EG_PS_RESOURCE__RESOURCE0_WORD0                0
+#define EG_PS_RESOURCE__RESOURCE0_WORD1                1
+#define EG_PS_RESOURCE__RESOURCE0_WORD2                2
+#define EG_PS_RESOURCE__RESOURCE0_WORD3                3
+#define EG_PS_RESOURCE__RESOURCE0_WORD4                4
+#define EG_PS_RESOURCE__RESOURCE0_WORD5                5
+#define EG_PS_RESOURCE__RESOURCE0_WORD6                6
+#define EG_PS_RESOURCE__RESOURCE0_WORD7                7
+#define EG_PS_RESOURCE_SIZE            8
+#define EG_PS_RESOURCE_PM4 128         
+
+/* EG_VS_RESOURCE */
+#define EG_VS_RESOURCE__RESOURCE160_WORD0              0
+#define EG_VS_RESOURCE__RESOURCE160_WORD1              1
+#define EG_VS_RESOURCE__RESOURCE160_WORD2              2
+#define EG_VS_RESOURCE__RESOURCE160_WORD3              3
+#define EG_VS_RESOURCE__RESOURCE160_WORD4              4
+#define EG_VS_RESOURCE__RESOURCE160_WORD5              5
+#define EG_VS_RESOURCE__RESOURCE160_WORD6              6
+#define EG_VS_RESOURCE__RESOURCE160_WORD7              7
+#define EG_VS_RESOURCE_SIZE            8
+#define EG_VS_RESOURCE_PM4 128         
+
+/* EG_FS_RESOURCE */
+#define EG_FS_RESOURCE__RESOURCE320_WORD0              0
+#define EG_FS_RESOURCE__RESOURCE320_WORD1              1
+#define EG_FS_RESOURCE__RESOURCE320_WORD2              2
+#define EG_FS_RESOURCE__RESOURCE320_WORD3              3
+#define EG_FS_RESOURCE__RESOURCE320_WORD4              4
+#define EG_FS_RESOURCE__RESOURCE320_WORD5              5
+#define EG_FS_RESOURCE__RESOURCE320_WORD6              6
+#define EG_FS_RESOURCE_SIZE            7
+#define EG_FS_RESOURCE_PM4 128         
+
+/* EG_GS_RESOURCE */
+#define EG_GS_RESOURCE__RESOURCE336_WORD0              0
+#define EG_GS_RESOURCE__RESOURCE336_WORD1              1
+#define EG_GS_RESOURCE__RESOURCE336_WORD2              2
+#define EG_GS_RESOURCE__RESOURCE336_WORD3              3
+#define EG_GS_RESOURCE__RESOURCE336_WORD4              4
+#define EG_GS_RESOURCE__RESOURCE336_WORD5              5
+#define EG_GS_RESOURCE__RESOURCE336_WORD6              6
+#define EG_GS_RESOURCE_SIZE            7
+#define EG_GS_RESOURCE_PM4 128         
+
+/* EG_PS_SAMPLER */
+#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0          0
+#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0          1
+#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0          2
+#define EG_PS_SAMPLER_SIZE             3
+#define EG_PS_SAMPLER_PM4 128          
+
+/* EG_VS_SAMPLER */
+#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18         0
+#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18         1
+#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18         2
+#define EG_VS_SAMPLER_SIZE             3
+#define EG_VS_SAMPLER_PM4 128          
+
+/* EG_GS_SAMPLER */
+#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36         0
+#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36         1
+#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36         2
+#define EG_GS_SAMPLER_SIZE             3
+#define EG_GS_SAMPLER_PM4 128          
+
+/* EG_PS_SAMPLER_BORDER */
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED                0
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN              1
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE               2
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA              3
+#define EG_PS_SAMPLER_BORDER_SIZE              4
+#define EG_PS_SAMPLER_BORDER_PM4 128           
+
+/* EG_VS_SAMPLER_BORDER */
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED                0
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN              1
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE               2
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA              3
+#define EG_VS_SAMPLER_BORDER_SIZE              4
+#define EG_VS_SAMPLER_BORDER_PM4 128           
+
+/* EG_GS_SAMPLER_BORDER */
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED                0
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN              1
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE               2
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA              3
+#define EG_GS_SAMPLER_BORDER_SIZE              4
+#define EG_GS_SAMPLER_BORDER_PM4 128           
+
+/* EG_CB0 */
+#define EG_CB0__CB_COLOR0_BASE         0
+#define EG_CB0__CB_COLOR0_PITCH                1
+#define EG_CB0__CB_COLOR0_SLICE                2
+#define EG_CB0__CB_COLOR0_VIEW         3
+#define EG_CB0__CB_COLOR0_INFO         4
+#define EG_CB0__CB_COLOR0_ATTRIB               5
+#define EG_CB0__CB_COLOR0_DIM          6
+#define EG_CB0_SIZE            7
+#define EG_CB0_PM4 128         
+
+/* EG_CB1 */
+#define EG_CB1__CB_COLOR1_BASE         0
+#define EG_CB1__CB_COLOR1_INFO         1
+#define EG_CB1__CB_COLOR1_SIZE         2
+#define EG_CB1__CB_COLOR1_VIEW         3
+#define EG_CB1__CB_COLOR1_FRAG         4
+#define EG_CB1__CB_COLOR1_TILE         5
+#define EG_CB1__CB_COLOR1_MASK         6
+#define EG_CB1_SIZE            7
+#define EG_CB1_PM4 128         
+
+/* EG_CB2 */
+#define EG_CB2__CB_COLOR2_BASE         0
+#define EG_CB2__CB_COLOR2_INFO         1
+#define EG_CB2__CB_COLOR2_SIZE         2
+#define EG_CB2__CB_COLOR2_VIEW         3
+#define EG_CB2__CB_COLOR2_FRAG         4
+#define EG_CB2__CB_COLOR2_TILE         5
+#define EG_CB2__CB_COLOR2_MASK         6
+#define EG_CB2_SIZE            7
+#define EG_CB2_PM4 128         
+
+/* EG_CB3 */
+#define EG_CB3__CB_COLOR3_BASE         0
+#define EG_CB3__CB_COLOR3_INFO         1
+#define EG_CB3__CB_COLOR3_SIZE         2
+#define EG_CB3__CB_COLOR3_VIEW         3
+#define EG_CB3__CB_COLOR3_FRAG         4
+#define EG_CB3__CB_COLOR3_TILE         5
+#define EG_CB3__CB_COLOR3_MASK         6
+#define EG_CB3_SIZE            7
+#define EG_CB3_PM4 128         
+
+/* EG_CB4 */
+#define EG_CB4__CB_COLOR4_BASE         0
+#define EG_CB4__CB_COLOR4_INFO         1
+#define EG_CB4__CB_COLOR4_SIZE         2
+#define EG_CB4__CB_COLOR4_VIEW         3
+#define EG_CB4__CB_COLOR4_FRAG         4
+#define EG_CB4__CB_COLOR4_TILE         5
+#define EG_CB4__CB_COLOR4_MASK         6
+#define EG_CB4_SIZE            7
+#define EG_CB4_PM4 128         
+
+/* EG_CB5 */
+#define EG_CB5__CB_COLOR5_BASE         0
+#define EG_CB5__CB_COLOR5_INFO         1
+#define EG_CB5__CB_COLOR5_SIZE         2
+#define EG_CB5__CB_COLOR5_VIEW         3
+#define EG_CB5__CB_COLOR5_FRAG         4
+#define EG_CB5__CB_COLOR5_TILE         5
+#define EG_CB5__CB_COLOR5_MASK         6
+#define EG_CB5_SIZE            7
+#define EG_CB5_PM4 128         
+
+/* EG_CB6 */
+#define EG_CB6__CB_COLOR6_BASE         0
+#define EG_CB6__CB_COLOR6_INFO         1
+#define EG_CB6__CB_COLOR6_SIZE         2
+#define EG_CB6__CB_COLOR6_VIEW         3
+#define EG_CB6__CB_COLOR6_FRAG         4
+#define EG_CB6__CB_COLOR6_TILE         5
+#define EG_CB6__CB_COLOR6_MASK         6
+#define EG_CB6_SIZE            7
+#define EG_CB6_PM4 128         
+
+/* EG_CB7 */
+#define EG_CB7__CB_COLOR7_BASE         0
+#define EG_CB7__CB_COLOR7_INFO         1
+#define EG_CB7__CB_COLOR7_SIZE         2
+#define EG_CB7__CB_COLOR7_VIEW         3
+#define EG_CB7__CB_COLOR7_FRAG         4
+#define EG_CB7__CB_COLOR7_TILE         5
+#define EG_CB7__CB_COLOR7_MASK         6
+#define EG_CB7_SIZE            7
+#define EG_CB7_PM4 128         
+
+/* EG_DB */
+#define EG_DB__DB_HTILE_DATA_BASE              0
+#define EG_DB__DB_Z_INFO               1
+#define EG_DB__DB_STENCIL_INFO         2
+#define EG_DB__DB_DEPTH_SIZE           3
+#define EG_DB__DB_DEPTH_SLICE          4
+#define EG_DB__DB_DEPTH_VIEW           5
+#define EG_DB__DB_HTILE_SURFACE                6
+#define EG_DB__DB_Z_READ_BASE          7
+#define EG_DB__DB_STENCIL_READ_BASE            8
+#define EG_DB__DB_Z_WRITE_BASE         9
+#define EG_DB__DB_STENCIL_WRITE_BASE           10
+#define EG_DB_SIZE             11
+#define EG_DB_PM4 128          
+
+/* EG_VGT */
+#define EG_VGT__VGT_PRIMITIVE_TYPE             0
+#define EG_VGT__VGT_MAX_VTX_INDX               1
+#define EG_VGT__VGT_MIN_VTX_INDX               2
+#define EG_VGT__VGT_INDX_OFFSET                3
+#define EG_VGT__VGT_DMA_INDEX_TYPE             4
+#define EG_VGT__VGT_PRIMITIVEID_EN             5
+#define EG_VGT__VGT_DMA_NUM_INSTANCES          6
+#define EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN             7
+#define EG_VGT__VGT_INSTANCE_STEP_RATE_0               8
+#define EG_VGT__VGT_INSTANCE_STEP_RATE_1               9
+#define EG_VGT_SIZE            10
+#define EG_VGT_PM4 128         
+
+/* EG_DRAW */
+#define EG_DRAW__VGT_NUM_INDICES               0
+#define EG_DRAW__VGT_DMA_BASE_HI               1
+#define EG_DRAW__VGT_DMA_BASE          2
+#define EG_DRAW__VGT_DRAW_INITIATOR            3
+#define EG_DRAW_SIZE           4
+#define EG_DRAW_PM4 128                
+
+/* EG_VGT_EVENT */
+#define EG_VGT_EVENT__VGT_EVENT_INITIATOR              0
+#define EG_VGT_EVENT_SIZE              1
+#define EG_VGT_EVENT_PM4 128           
+
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
new file mode 100644 (file)
index 0000000..6fab221
--- /dev/null
@@ -0,0 +1,1442 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef EVERGREEND_H
+#define EVERGREEND_H
+
+#define R600_TEXEL_PITCH_ALIGNMENT_MASK        0x7
+
+#define PKT3_NOP                               0x10
+#define PKT3_INDIRECT_BUFFER_END               0x17
+#define PKT3_SET_PREDICATION                   0x20
+#define PKT3_REG_RMW                           0x21
+#define PKT3_COND_EXEC                         0x22
+#define PKT3_PRED_EXEC                         0x23
+#define PKT3_START_3D_CMDBUF                   0x24
+#define PKT3_DRAW_INDEX_2                      0x27
+#define PKT3_CONTEXT_CONTROL                   0x28
+#define PKT3_DRAW_INDEX_IMMD_BE                0x29
+#define PKT3_INDEX_TYPE                        0x2A
+#define PKT3_DRAW_INDEX                        0x2B
+#define PKT3_DRAW_INDEX_AUTO                   0x2D
+#define PKT3_DRAW_INDEX_IMMD                   0x2E
+#define PKT3_NUM_INSTANCES                     0x2F
+#define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_INDIRECT_BUFFER_MP                0x38
+#define PKT3_MEM_SEMAPHORE                     0x39
+#define PKT3_MPEG_INDEX                        0x3A
+#define PKT3_WAIT_REG_MEM                      0x3C
+#define PKT3_MEM_WRITE                         0x3D
+#define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_CP_INTERRUPT                      0x40
+#define PKT3_SURFACE_SYNC                      0x43
+#define PKT3_ME_INITIALIZE                     0x44
+#define PKT3_COND_WRITE                        0x45
+#define PKT3_EVENT_WRITE                       0x46
+#define PKT3_EVENT_WRITE_EOP                   0x47
+#define PKT3_ONE_REG_WRITE                     0x57
+#define PKT3_SET_CONFIG_REG                    0x68
+#define PKT3_SET_CONTEXT_REG                   0x69
+#define PKT3_SET_ALU_CONST                     0x6A
+#define PKT3_SET_BOOL_CONST                    0x6B
+#define PKT3_SET_LOOP_CONST                    0x6C
+#define PKT3_SET_RESOURCE                      0x6D
+#define PKT3_SET_SAMPLER                       0x6E
+#define PKT3_SET_CTL_CONST                     0x6F
+#define PKT3_SURFACE_BASE_UPDATE               0x73
+
+#define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
+#define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
+#define PKT_TYPE_C                      0x3FFFFFFF
+#define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
+#define PKT_COUNT_G(x)                  (((x) >> 16) & 0x3FFF)
+#define PKT_COUNT_C                     0xC000FFFF
+#define PKT0_BASE_INDEX_S(x)            (((x) & 0xFFFF) << 0)
+#define PKT0_BASE_INDEX_G(x)            (((x) >> 0) & 0xFFFF)
+#define PKT0_BASE_INDEX_C               0xFFFF0000
+#define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
+#define PKT3_IT_OPCODE_G(x)             (((x) >> 8) & 0xFF)
+#define PKT3_IT_OPCODE_C                0xFFFF00FF
+#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
+#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count))
+
+/* Registers */
+#define R_008C00_SQ_CONFIG                           0x00008C00
+#define   S_008C00_VC_ENABLE(x)                        (((x) & 0x1) << 0)
+#define   G_008C00_VC_ENABLE(x)                        (((x) >> 0) & 0x1)
+#define   C_008C00_VC_ENABLE(x)                        0xFFFFFFFE
+#define   S_008C00_EXPORT_SRC_C(x)                     (((x) & 0x1) << 1)
+#define   G_008C00_EXPORT_SRC_C(x)                     (((x) >> 1) & 0x1)
+#define   C_008C00_EXPORT_SRC_C(x)                     0xFFFFFFFD
+/* different */
+#define   S_008C00_CS_PRIO(x)                          (((x) & 0x3) << 18)
+#define   G_008C00_CS_PRIO(x)                          (((x) >> 18) & 0x3)
+#define   C_008C00_CS_PRIO(x)                          0xFFF3FFFF
+#define   S_008C00_LS_PRIO(x)                          (((x) & 0x3) << 20)
+#define   G_008C00_LS_PRIO(x)                          (((x) >> 20) & 0x3)
+#define   C_008C00_LS_PRIO(x)                          0xFFCFFFFF
+#define   S_008C00_HS_PRIO(x)                          (((x) & 0x3) << 22)
+#define   G_008C00_HS_PRIO(x)                          (((x) >> 22) & 0x3)
+#define   C_008C00_HS_PRIO(x)                          0xFF3FFFFF
+#define   S_008C00_PS_PRIO(x)                          (((x) & 0x3) << 24)
+#define   G_008C00_PS_PRIO(x)                          (((x) >> 24) & 0x3)
+#define   C_008C00_PS_PRIO(x)                          0xFCFFFFFF
+#define   S_008C00_VS_PRIO(x)                          (((x) & 0x3) << 26)
+#define   G_008C00_VS_PRIO(x)                          (((x) >> 26) & 0x3)
+#define   C_008C00_VS_PRIO(x)                          0xF3FFFFFF
+#define   S_008C00_GS_PRIO(x)                          (((x) & 0x3) << 28)
+#define   G_008C00_GS_PRIO(x)                          (((x) >> 28) & 0x3)
+#define   C_008C00_GS_PRIO(x)                          0xCFFFFFFF
+#define   S_008C00_ES_PRIO(x)                          (((x) & 0x3) << 30)
+#define   G_008C00_ES_PRIO(x)                          (((x) >> 30) & 0x3)
+#define   C_008C00_ES_PRIO(x)                          0x3FFFFFFF
+#define R_008C04_SQ_GPR_RESOURCE_MGMT_1              0x00008C04
+#define   S_008C04_NUM_PS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C04_NUM_PS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C04_NUM_PS_GPRS(x)                      0xFFFFFF00
+#define   S_008C04_NUM_VS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C04_NUM_VS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C04_NUM_VS_GPRS(x)                      0xFF00FFFF
+#define   S_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) & 0xF) << 28)
+#define   G_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) >> 28) & 0xF)
+#define   C_008C04_NUM_CLAUSE_TEMP_GPRS(x)             0x0FFFFFFF
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x00008C08
+#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C08_NUM_GS_GPRS(x)                      0xFFFFFF00
+#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C08_NUM_ES_GPRS(x)                      0xFF00FFFF
+#define R_008C0C_SQ_GPR_RESOURCE_MGMT_3              0x00008C0C
+#define   S_008C0C_NUM_HS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C0C_NUM_HS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C0C_NUM_HS_GPRS(x)                      0xFFFFFF00
+#define   S_008C0C_NUM_LS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C0C_NUM_LS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C0C_NUM_LS_GPRS(x)                      0xFF00FFFF
+#define R_008C18_SQ_THREAD_RESOURCE_MGMT_1           0x00008C18
+#define   S_008C18_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C18_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C18_NUM_PS_THREADS(x)                   0xFFFFFF00
+#define   S_008C18_NUM_VS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C18_NUM_VS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C18_NUM_VS_THREADS(x)                   0xFFFF00FF
+#define   S_008C18_NUM_GS_THREADS(x)                   (((x) & 0xFF) << 16)
+#define   G_008C18_NUM_GS_THREADS(x)                   (((x) >> 16) & 0xFF)
+#define   C_008C18_NUM_GS_THREADS(x)                   0xFF00FFFF
+#define   S_008C18_NUM_ES_THREADS(x)                   (((x) & 0xFF) << 24)
+#define   G_008C18_NUM_ES_THREADS(x)                   (((x) >> 24) & 0xFF)
+#define   C_008C18_NUM_ES_THREADS(x)                   0x00FFFFFF
+#define R_008C1C_SQ_THREAD_RESOURCE_MGMT_2             0x00008C1C
+#define   S_008C1C_NUM_HS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C1C_NUM_HS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C1C_NUM_HS_THREADS(x)                   0xFFFFFF00
+#define   S_008C1C_NUM_LS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C1C_NUM_LS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C1C_NUM_LS_THREADS(x)                   0xFFFF00FF
+#define R_008C20_SQ_STACK_RESOURCE_MGMT_1            0x00008C20
+#define   S_008C20_NUM_PS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C20_NUM_PS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C20_NUM_PS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C20_NUM_VS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C20_NUM_VS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C20_NUM_VS_STACK_ENTRIES(x)             0xF000FFFF
+#define R_008C24_SQ_STACK_RESOURCE_MGMT_2            0x00008C24
+#define   S_008C24_NUM_GS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C24_NUM_GS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C24_NUM_GS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C24_NUM_ES_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C24_NUM_ES_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C24_NUM_ES_STACK_ENTRIES(x)             0xF000FFFF
+#define R_008C28_SQ_STACK_RESOURCE_MGMT_3            0x00008C28
+#define   S_008C28_NUM_HS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C28_NUM_HS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C28_NUM_HS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C28_NUM_LS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C28_NUM_LS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C28_NUM_LS_STACK_ENTRIES(x)             0xF000FFFF
+
+#define R_008CF0_SQ_MS_FIFO_SIZES                     0x00008CF0
+#define   S_008CF0_CACHE_FIFO_SIZE(x)                  (((x) & 0xFF) << 0)
+#define   G_008CF0_CACHE_FIFO_SIZE(x)                  (((x) >> 0) & 0xFF)
+#define   C_008CF0_CACHE_FIFO_SIZE(x)                  0xFFFFFF00
+#define   S_008CF0_FETCH_FIFO_HIWATER(x)               (((x) & 0x1F) << 8)
+#define   G_008CF0_FETCH_FIFO_HIWATER(x)               (((x) >> 8) & 0x1F)
+#define   C_008CF0_FETCH_FIFO_HIWATER(x)               0xFFFFE0FF
+#define   S_008CF0_DONE_FIFO_HIWATER(x)                (((x) & 0xFF) << 16)
+#define   G_008CF0_DONE_FIFO_HIWATER(x)                (((x) >> 16) & 0xFF)
+#define   C_008CF0_DONE_FIFO_HIWATER(x)                0xFF00FFFF
+#define   S_008CF0_ALU_UPDATE_FIFO_HIWATER(x)          (((x) & 0x1F) << 24)
+#define   G_008CF0_ALU_UPDATE_FIFO_HIWATER(x)          (((x) >> 24) & 0x1F)
+#define   C_008CF0_ALU_UPDATE_FIFO_HIWATER(x)          0xE0FFFFFF
+
+#define R_009100_SPI_CONFIG_CNTL                      0x00009100
+#define R_00913C_SPI_CONFIG_CNTL_1                    0x0000913C
+#define   S_00913C_VTX_DONE_DELAY(x)                (((x) & 0xF) << 0)
+#define   G_00913C_VTX_DONE_DELAY(x)                (((x) >> 0) & 0xF )
+#define   C_00913C_VTX_DONE_DELAY(x)                0xFFFFFFF0
+
+
+#define R_028C64_CB_COLOR0_PITCH                      0x028C64
+#define   S_028C64_PITCH_TILE_MAX(x)                   (((x) & 0x7FF) << 0)
+#define   G_028C64_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x7FF)
+#define   C_028C64_PITCH_TILE_MAX                      0xFFFFF800
+#define R_028C68_CB_COLOR0_SLICE                      0x028C68
+#define   S_028C68_SLICE_TILE_MAX(x)                   (((x) & 0x3FFFFF) << 0)
+#define   G_028C68_SLICE_TILE_MAX(x)                   (((x) >> 0) & 0x3FFFFF)
+#define   C_028C68_SLICE_TILE_MAX                      0xFFC00000
+#define R_028C70_CB_COLOR0_INFO                      0x028C70
+#define   S_028C70_ENDIAN(x)                           (((x) & 0x3) << 0)
+#define   G_028C70_ENDIAN(x)                           (((x) >> 0) & 0x3)
+#define   C_028C70_ENDIAN                              0xFFFFFFFC
+#define   S_028C70_FORMAT(x)                           (((x) & 0x3F) << 2)
+#define   G_028C70_FORMAT(x)                           (((x) >> 2) & 0x3F)
+#define   C_028C70_FORMAT                              0xFFFFFF03
+#define     V_028C70_COLOR_INVALID                     0x00000000
+#define     V_028C70_COLOR_8                           0x00000001
+#define     V_028C70_COLOR_4_4                         0x00000002
+#define     V_028C70_COLOR_3_3_2                       0x00000003
+#define     V_028C70_COLOR_16                          0x00000005
+#define     V_028C70_COLOR_16_FLOAT                    0x00000006
+#define     V_028C70_COLOR_8_8                         0x00000007
+#define     V_028C70_COLOR_5_6_5                       0x00000008
+#define     V_028C70_COLOR_6_5_5                       0x00000009
+#define     V_028C70_COLOR_1_5_5_5                     0x0000000A
+#define     V_028C70_COLOR_4_4_4_4                     0x0000000B
+#define     V_028C70_COLOR_5_5_5_1                     0x0000000C
+#define     V_028C70_COLOR_32                          0x0000000D
+#define     V_028C70_COLOR_32_FLOAT                    0x0000000E
+#define     V_028C70_COLOR_16_16                       0x0000000F
+#define     V_028C70_COLOR_16_16_FLOAT                 0x00000010
+#define     V_028C70_COLOR_8_24                        0x00000011
+#define     V_028C70_COLOR_8_24_FLOAT                  0x00000012
+#define     V_028C70_COLOR_24_8                        0x00000013
+#define     V_028C70_COLOR_24_8_FLOAT                  0x00000014
+#define     V_028C70_COLOR_10_11_11                    0x00000015
+#define     V_028C70_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_028C70_COLOR_11_11_10                    0x00000017
+#define     V_028C70_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_028C70_COLOR_2_10_10_10                  0x00000019
+#define     V_028C70_COLOR_8_8_8_8                     0x0000001A
+#define     V_028C70_COLOR_10_10_10_2                  0x0000001B
+#define     V_028C70_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_028C70_COLOR_32_32                       0x0000001D
+#define     V_028C70_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_028C70_COLOR_16_16_16_16                 0x0000001F
+#define     V_028C70_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_028C70_COLOR_32_32_32_32                 0x00000022
+#define     V_028C70_COLOR_32_32_32_32_FLOAT           0x00000023
+#define     V_028C70_COLOR_32_32_32_FLOAT              0x00000030
+#define   S_028C70_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
+#define   G_028C70_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
+#define   C_028C70_ARRAY_MODE                          0xFFFFF0FF
+#define     V_028C70_ARRAY_LINEAR_GENERAL              0x00000000
+#define     V_028C70_ARRAY_LINEAR_ALIGNED              0x00000001
+#define     V_028C70_ARRAY_1D_TILED_THIN1              0x00000002
+#define     V_028C70_ARRAY_2D_TILED_THIN1              0x00000004
+#define   S_028C70_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
+#define   G_028C70_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
+#define   C_028C70_NUMBER_TYPE                         0xFFFF8FFF
+#define     V_028C70_NUMBER_UNORM                      0x00000000
+#define     V_028C70_NUMBER_SNORM                      0x00000001
+#define     V_028C70_NUMBER_USCALED                    0x00000002
+#define     V_028C70_NUMBER_SSCALED                    0x00000003
+#define     V_028C70_NUMBER_UINT                       0x00000004
+#define     V_028C70_NUMBER_SINT                       0x00000005
+#define     V_028C70_NUMBER_SRGB                       0x00000006
+#define     V_028C70_NUMBER_FLOAT                      0x00000007
+#define   S_028C70_COMP_SWAP(x)                        (((x) & 0x3) << 15)
+#define   G_028C70_COMP_SWAP(x)                        (((x) >> 15) & 0x3)
+#define   C_028C70_COMP_SWAP                           0xFFFE7FFF
+#define     V_028C70_SWAP_STD                          0x00000000
+#define     V_028C70_SWAP_ALT                          0x00000001
+#define     V_028C70_SWAP_STD_REV                      0x00000002
+#define     V_028C70_SWAP_ALT_REV                      0x00000003
+#define   S_028C70_FAST_CLEAR(x)                       (((x) & 0x1) << 17)
+#define   G_028C70_FAST_CLEAR(x)                       (((x) >> 17) & 0x1)
+#define   C_028C70_FAST_CLEAR                          0xFFFDFFFF
+#define   S_028C70_COMPRESSION(x)                      (((x) & 0x3) << 18)
+#define   G_028C70_COMPRESSION(x)                      (((x) >> 18) & 0x3)
+#define   C_028C70_COMPRESSION                         0xFFF3FFFF
+#define   S_028C70_BLEND_CLAMP(x)                      (((x) & 0x1) << 19)
+#define   G_028C70_BLEND_CLAMP(x)                      (((x) >> 19) & 0x1)
+#define   C_028C70_BLEND_CLAMP                         0xFFF7FFFF
+#define   S_028C70_BLEND_BYPASS(x)                     (((x) & 0x1) << 20)
+#define   G_028C70_BLEND_BYPASS(x)                     (((x) >> 20) & 0x1)
+#define   C_028C70_BLEND_BYPASS                        0xFFEFFFFF
+#define   S_028C70_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 21)
+#define   G_028C70_SIMPLE_FLOAT(x)                     (((x) >> 21) & 0x1)
+#define   C_028C70_SIMPLE_FLOAT                        0xFFDFFFFF
+#define   S_028C70_ROUND_MODE(x)                       (((x) & 0x1) << 22)
+#define   G_028C70_ROUND_MODE(x)                       (((x) >> 22) & 0x1)
+#define   C_028C70_ROUND_MODE                          0xFFBFFFFF
+#define   S_028C70_TILE_COMPACT(x)                     (((x) & 0x1) << 23)
+#define   G_028C70_TILE_COMPACT(x)                     (((x) >> 23) & 0x1)
+#define   C_028C70_TILE_COMPACT                        0xFF7FFFFF
+#define   S_028C70_SOURCE_FORMAT(x)                    (((x) & 0x3) << 24)
+#define   G_028C70_SOURCE_FORMAT(x)                    (((x) >> 24) & 0x3)
+#define   C_028C70_SOURCE_FORMAT                       0xFCFFFFFF
+#define   S_028C70_RAT(x)                              (((x) & 0x1) << 26)
+#define   G_028C70_RAT(x)                              (((x) >> 26) & 0x1)
+#define   C_028C70_RAT                                 0xFBFFFFFF
+#define   S_028C70_RESOURCE_TYPE(x)                    (((x) & 0x7) << 27)
+#define   G_028C70_RESOURCE_TYPE(x)                    (((x) >> 27) & 0x7)
+#define   C_028C70_RESOURCE_TYPE                       0xC7FFFFFF
+
+#define R_028C74_CB_COLOR0_ATTRIB                      0x028C74
+#define   S_028C74_NON_DISP_TILING_ORDER(x)            (((x) & 0x1) << 4)
+#define   G_028C74_NON_DISP_TILING_ORDER(x)            (((x) >> 4) & 0x1)
+#define   C_028C74_NON_DISP_TILING_ORDER               0xFFFFFFEF
+#define R_028C78_CB_COLOR0_DIM                         0x028C78
+#define   S_028C78_WIDTH_MAX(x)                        (((x) & 0xFFFF) << 0)
+#define   G_028C78_WIDTH_MAX(x)                        (((x) >> 0) & 0xFFFF)
+#define   C_028C78_WIDTH_MAX                           0xFFFF0000
+#define   S_028C78_HEIGHT_MAX(x)                       (((x) & 0xFFFF) << 16)
+#define   G_028C78_HEIGHT_MAX(x)                       (((x) >> 16) & 0xFFFF)
+#define   C_028C78_HEIGHT_MAX                          0x0000FFFF
+
+#define R_028C7C_CB_COLOR0_CMASK                         0x028C7C
+#define R_028C80_CB_COLOR0_CMASK_SLICE                   0x028C80
+#define R_028C84_CB_COLOR0_FMASK                         0x028C84
+#define R_028C88_CB_COLOR0_FMASK_SLICE                   0x028C88
+
+#define R_028C8C_CB_COLOR0_CLEAR_WORD0                   0x028C8C
+#define R_028C90_CB_COLOR0_CLEAR_WORD1                   0x028C90
+#define R_028C94_CB_COLOR0_CLEAR_WORD2                   0x028C94
+#define R_028C98_CB_COLOR0_CLEAR_WORD3                   0x028C98
+
+/* alpha same */
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
+
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
+#define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
+#define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
+#define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
+#define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
+#define   C_028800_Z_ENABLE                            0xFFFFFFFD
+#define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
+#define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
+#define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
+#define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
+#define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
+#define   C_028800_ZFUNC                               0xFFFFFF8F
+#define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
+#define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
+#define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
+#define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
+#define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
+#define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define     V_028800_STENCILFUNC_NEVER                 0x00000000
+#define     V_028800_STENCILFUNC_LESS                  0x00000001
+#define     V_028800_STENCILFUNC_EQUAL                 0x00000002
+#define     V_028800_STENCILFUNC_LEQUAL                0x00000003
+#define     V_028800_STENCILFUNC_GREATER               0x00000004
+#define     V_028800_STENCILFUNC_NOTEQUAL              0x00000005
+#define     V_028800_STENCILFUNC_GEQUAL                0x00000006
+#define     V_028800_STENCILFUNC_ALWAYS                0x00000007
+#define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
+#define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
+#define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define     V_028800_STENCIL_KEEP                      0x00000000
+#define     V_028800_STENCIL_ZERO                      0x00000001
+#define     V_028800_STENCIL_REPLACE                   0x00000002
+#define     V_028800_STENCIL_INCR                      0x00000003
+#define     V_028800_STENCIL_DECR                      0x00000004
+#define     V_028800_STENCIL_INVERT                    0x00000005
+#define     V_028800_STENCIL_INCR_WRAP                 0x00000006
+#define     V_028800_STENCIL_DECR_WRAP                 0x00000007
+#define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
+#define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
+#define   C_028800_STENCILZPASS                        0xFFFE3FFF
+#define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
+#define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
+#define   C_028800_STENCILZFAIL                        0xFFF1FFFF
+#define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
+#define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
+#define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
+#define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
+#define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
+#define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
+#define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
+#define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
+#define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
+#define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
+#define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
+#define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_MODE(x)                             (((x) & 0x7) << 4)
+#define   G_028808_MODE(x)                             (((x) >> 4) & 0x7)
+#define   C_028808_MODE                                0xFFFFFF8F
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
+#define R_028810_PA_CL_CLIP_CNTL                     0x028810
+#define   S_028810_UCP_ENA_0(x)                        (((x) & 0x1) << 0)
+#define   G_028810_UCP_ENA_0(x)                        (((x) >> 0) & 0x1)
+#define   C_028810_UCP_ENA_0                           0xFFFFFFFE
+#define   S_028810_UCP_ENA_1(x)                        (((x) & 0x1) << 1)
+#define   G_028810_UCP_ENA_1(x)                        (((x) >> 1) & 0x1)
+#define   C_028810_UCP_ENA_1                           0xFFFFFFFD
+#define   S_028810_UCP_ENA_2(x)                        (((x) & 0x1) << 2)
+#define   G_028810_UCP_ENA_2(x)                        (((x) >> 2) & 0x1)
+#define   C_028810_UCP_ENA_2                           0xFFFFFFFB
+#define   S_028810_UCP_ENA_3(x)                        (((x) & 0x1) << 3)
+#define   G_028810_UCP_ENA_3(x)                        (((x) >> 3) & 0x1)
+#define   C_028810_UCP_ENA_3                           0xFFFFFFF7
+#define   S_028810_UCP_ENA_4(x)                        (((x) & 0x1) << 4)
+#define   G_028810_UCP_ENA_4(x)                        (((x) >> 4) & 0x1)
+#define   C_028810_UCP_ENA_4                           0xFFFFFFEF
+#define   S_028810_UCP_ENA_5(x)                        (((x) & 0x1) << 5)
+#define   G_028810_UCP_ENA_5(x)                        (((x) >> 5) & 0x1)
+#define   C_028810_UCP_ENA_5                           0xFFFFFFDF
+#define   S_028810_PS_UCP_Y_SCALE_NEG(x)               (((x) & 0x1) << 13)
+#define   G_028810_PS_UCP_Y_SCALE_NEG(x)               (((x) >> 13) & 0x1)
+#define   C_028810_PS_UCP_Y_SCALE_NEG                  0xFFFFDFFF
+#define   S_028810_PS_UCP_MODE(x)                      (((x) & 0x3) << 14)
+#define   G_028810_PS_UCP_MODE(x)                      (((x) >> 14) & 0x3)
+#define   C_028810_PS_UCP_MODE                         0xFFFF3FFF
+#define   S_028810_CLIP_DISABLE(x)                     (((x) & 0x1) << 16)
+#define   G_028810_CLIP_DISABLE(x)                     (((x) >> 16) & 0x1)
+#define   C_028810_CLIP_DISABLE                        0xFFFEFFFF
+#define   S_028810_UCP_CULL_ONLY_ENA(x)                (((x) & 0x1) << 17)
+#define   G_028810_UCP_CULL_ONLY_ENA(x)                (((x) >> 17) & 0x1)
+#define   C_028810_UCP_CULL_ONLY_ENA                   0xFFFDFFFF
+#define   S_028810_BOUNDARY_EDGE_FLAG_ENA(x)           (((x) & 0x1) << 18)
+#define   G_028810_BOUNDARY_EDGE_FLAG_ENA(x)           (((x) >> 18) & 0x1)
+#define   C_028810_BOUNDARY_EDGE_FLAG_ENA              0xFFFBFFFF
+#define   S_028810_DX_CLIP_SPACE_DEF(x)                (((x) & 0x1) << 19)
+#define   G_028810_DX_CLIP_SPACE_DEF(x)                (((x) >> 19) & 0x1)
+#define   C_028810_DX_CLIP_SPACE_DEF                   0xFFF7FFFF
+#define   S_028810_DIS_CLIP_ERR_DETECT(x)              (((x) & 0x1) << 20)
+#define   G_028810_DIS_CLIP_ERR_DETECT(x)              (((x) >> 20) & 0x1)
+#define   C_028810_DIS_CLIP_ERR_DETECT                 0xFFEFFFFF
+#define   S_028810_VTX_KILL_OR(x)                      (((x) & 0x1) << 21)
+#define   G_028810_VTX_KILL_OR(x)                      (((x) >> 21) & 0x1)
+#define   C_028810_VTX_KILL_OR                         0xFFDFFFFF
+#define   S_028810_DX_LINEAR_ATTR_CLIP_ENA(x)          (((x) & 0x1) << 24)
+#define   G_028810_DX_LINEAR_ATTR_CLIP_ENA(x)          (((x) >> 24) & 0x1)
+#define   C_028810_DX_LINEAR_ATTR_CLIP_ENA             0xFEFFFFFF
+#define   S_028810_VTE_VPORT_PROVOKE_DISABLE(x)        (((x) & 0x1) << 25)
+#define   G_028810_VTE_VPORT_PROVOKE_DISABLE(x)        (((x) >> 25) & 0x1)
+#define   C_028810_VTE_VPORT_PROVOKE_DISABLE           0xFDFFFFFF
+#define   S_028810_ZCLIP_NEAR_DISABLE(x)               (((x) & 0x1) << 26)
+#define   G_028810_ZCLIP_NEAR_DISABLE(x)               (((x) >> 26) & 0x1)
+#define   C_028810_ZCLIP_NEAR_DISABLE                  0xFBFFFFFF
+#define   S_028810_ZCLIP_FAR_DISABLE(x)                (((x) & 0x1) << 27)
+#define   G_028810_ZCLIP_FAR_DISABLE(x)                (((x) >> 27) & 0x1)
+#define   C_028810_ZCLIP_FAR_DISABLE                   0xF7FFFFFF
+
+#define R_028040_DB_Z_INFO                       0x028040
+#define   S_028040_FORMAT(x)                           (((x) & 0x3) << 0)
+#define   G_028040_FORMAT(x)                           (((x) >> 0) & 0x3)
+#define   C_028040_FORMAT                              0xFFFFFFFC
+#define     V_028040_Z_INVALID                     0x00000000
+#define     V_028040_Z_16                          0x00000001
+#define     V_028040_Z_24                          0x00000002
+#define     V_028040_Z_32_FLOAT                    0x00000003
+#define   S_028040_ARRAY_MODE(x)                       (((x) & 0xF) << 4)
+#define   G_028040_ARRAY_MODE(x)                       (((x) >> 4) & 0xF)
+#define   C_028040_ARRAY_MODE                          0xFFFFFF0F
+#define   S_028040_READ_SIZE(x)                        (((x) & 0x1) << 28)
+#define   G_028040_READ_SIZE(x)                        (((x) >> 28) & 0x1)
+#define   C_028040_READ_SIZE                           0xEFFFFFFF
+#define   S_028040_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 29)
+#define   G_028040_TILE_SURFACE_ENABLE(x)              (((x) >> 29) & 0x1)
+#define   C_028040_TILE_SURFACE_ENABLE                 0xDFFFFFFF
+#define   S_028040_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
+#define   G_028040_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
+#define   C_028040_ZRANGE_PRECISION                    0x7FFFFFFF
+
+#define R_028044_DB_STENCIL_INFO                     0x028044
+#define   S_028044_FORMAT(x)                           (((x) & 0x1) << 0)
+#define   G_028044_FORMAT(x)                           (((x) >> 0) & 0x1)
+#define   C_028044_FORMAT                              0xFFFFFFFE
+
+#define R_028058_DB_DEPTH_SIZE                       0x028058
+#define   S_028058_PITCH_TILE_MAX(x)                   (((x) & 0x7FF) << 0)
+#define   G_028058_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x7FF)
+#define   C_028058_PITCH_TILE_MAX                      0xFFFFF800
+#define   S_028058_HEIGHT_TILE_MAX(x)                   (((x) & 0x7FF) << 11)
+#define   G_028058_HEIGHT_TILE_MAX(x)                   (((x) >> 11) & 0x7FF)
+#define   C_028058_HEIGHT_TILE_MAX                      0xFFC007FF
+
+#define R_02805C_DB_DEPTH_SLICE                      0x02805C
+#define   S_02805C_SLICE_TILE_MAX(x)                   (((x) & 0x3FFFFF) << 0)
+#define   G_02805C_SLICE_TILE_MAX(x)                   (((x) >> 0) & 0x3FFFFF)
+#define   C_02805C_SLICE_TILE_MAX                      0xFFC00000
+
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define   S_028430_STENCILREF(x)                       (((x) & 0xFF) << 0)
+#define   G_028430_STENCILREF(x)                       (((x) >> 0) & 0xFF)
+#define   C_028430_STENCILREF                          0xFFFFFF00
+#define   S_028430_STENCILMASK(x)                      (((x) & 0xFF) << 8)
+#define   G_028430_STENCILMASK(x)                      (((x) >> 8) & 0xFF)
+#define   C_028430_STENCILMASK                         0xFFFF00FF
+#define   S_028430_STENCILWRITEMASK(x)                 (((x) & 0xFF) << 16)
+#define   G_028430_STENCILWRITEMASK(x)                 (((x) >> 16) & 0xFF)
+#define   C_028430_STENCILWRITEMASK                    0xFF00FFFF
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define   S_028434_STENCILREF_BF(x)                    (((x) & 0xFF) << 0)
+#define   G_028434_STENCILREF_BF(x)                    (((x) >> 0) & 0xFF)
+#define   C_028434_STENCILREF_BF                       0xFFFFFF00
+#define   S_028434_STENCILMASK_BF(x)                   (((x) & 0xFF) << 8)
+#define   G_028434_STENCILMASK_BF(x)                   (((x) >> 8) & 0xFF)
+#define   C_028434_STENCILMASK_BF                      0xFFFF00FF
+#define   S_028434_STENCILWRITEMASK_BF(x)              (((x) & 0xFF) << 16)
+#define   G_028434_STENCILWRITEMASK_BF(x)              (((x) >> 16) & 0xFF)
+#define   C_028434_STENCILWRITEMASK_BF                 0xFF00FFFF
+#define R_028780_CB_BLEND_CONTROL                    0x028780
+#define   S_028780_COLOR_SRCBLEND(x)                   (((x) & 0x1F) << 0)
+#define   G_028780_COLOR_SRCBLEND(x)                   (((x) >> 0) & 0x1F)
+#define   C_028780_COLOR_SRCBLEND                      0xFFFFFFE0
+#define     V_028780_BLEND_ZERO                        0x00000000
+#define     V_028780_BLEND_ONE                         0x00000001
+#define     V_028780_BLEND_SRC_COLOR                   0x00000002
+#define     V_028780_BLEND_ONE_MINUS_SRC_COLOR         0x00000003
+#define     V_028780_BLEND_SRC_ALPHA                   0x00000004
+#define     V_028780_BLEND_ONE_MINUS_SRC_ALPHA         0x00000005
+#define     V_028780_BLEND_DST_ALPHA                   0x00000006
+#define     V_028780_BLEND_ONE_MINUS_DST_ALPHA         0x00000007
+#define     V_028780_BLEND_DST_COLOR                   0x00000008
+#define     V_028780_BLEND_ONE_MINUS_DST_COLOR         0x00000009
+#define     V_028780_BLEND_SRC_ALPHA_SATURATE          0x0000000A
+#define     V_028780_BLEND_BOTH_SRC_ALPHA              0x0000000B
+#define     V_028780_BLEND_BOTH_INV_SRC_ALPHA          0x0000000C
+#define     V_028780_BLEND_CONST_COLOR                 0x0000000D
+#define     V_028780_BLEND_ONE_MINUS_CONST_COLOR       0x0000000E
+#define     V_028780_BLEND_SRC1_COLOR                  0x0000000F
+#define     V_028780_BLEND_INV_SRC1_COLOR              0x00000010
+#define     V_028780_BLEND_SRC1_ALPHA                  0x00000011
+#define     V_028780_BLEND_INV_SRC1_ALPHA              0x00000012
+#define     V_028780_BLEND_CONST_ALPHA                 0x00000013
+#define     V_028780_BLEND_ONE_MINUS_CONST_ALPHA       0x00000014
+#define   S_028780_COLOR_COMB_FCN(x)                   (((x) & 0x7) << 5)
+#define   G_028780_COLOR_COMB_FCN(x)                   (((x) >> 5) & 0x7)
+#define   C_028780_COLOR_COMB_FCN                      0xFFFFFF1F
+#define     V_028780_COMB_DST_PLUS_SRC                 0x00000000
+#define     V_028780_COMB_SRC_MINUS_DST                0x00000001
+#define     V_028780_COMB_MIN_DST_SRC                  0x00000002
+#define     V_028780_COMB_MAX_DST_SRC                  0x00000003
+#define     V_028780_COMB_DST_MINUS_SRC                0x00000004
+#define   S_028780_COLOR_DESTBLEND(x)                  (((x) & 0x1F) << 8)
+#define   G_028780_COLOR_DESTBLEND(x)                  (((x) >> 8) & 0x1F)
+#define   C_028780_COLOR_DESTBLEND                     0xFFFFE0FF
+#define   S_028780_OPACITY_WEIGHT(x)                   (((x) & 0x1) << 13)
+#define   G_028780_OPACITY_WEIGHT(x)                   (((x) >> 13) & 0x1)
+#define   C_028780_OPACITY_WEIGHT                      0xFFFFDFFF
+#define   S_028780_ALPHA_SRCBLEND(x)                   (((x) & 0x1F) << 16)
+#define   G_028780_ALPHA_SRCBLEND(x)                   (((x) >> 16) & 0x1F)
+#define   C_028780_ALPHA_SRCBLEND                      0xFFE0FFFF
+#define   S_028780_ALPHA_COMB_FCN(x)                   (((x) & 0x7) << 21)
+#define   G_028780_ALPHA_COMB_FCN(x)                   (((x) >> 21) & 0x7)
+#define   C_028780_ALPHA_COMB_FCN                      0xFF1FFFFF
+#define   S_028780_ALPHA_DESTBLEND(x)                  (((x) & 0x1F) << 24)
+#define   G_028780_ALPHA_DESTBLEND(x)                  (((x) >> 24) & 0x1F)
+#define   C_028780_ALPHA_DESTBLEND                     0xE0FFFFFF
+#define   S_028780_SEPARATE_ALPHA_BLEND(x)             (((x) & 0x1) << 29)
+#define   G_028780_SEPARATE_ALPHA_BLEND(x)             (((x) >> 29) & 0x1)
+#define   C_028780_SEPARATE_ALPHA_BLEND                0xDFFFFFFF
+#define   S_028780_BLEND_CONTROL_ENABLE(x)             (((x) & 0x1) << 30)
+#define   G_028780_BLEND_CONTROL_ENABLE(x)             (((x) >> 30) & 0x1)
+#define   C_028780_BLEND_CONTROL_ENABLE                0xEFFFFFFF
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define   S_028814_CULL_FRONT(x)                       (((x) & 0x1) << 0)
+#define   G_028814_CULL_FRONT(x)                       (((x) >> 0) & 0x1)
+#define   C_028814_CULL_FRONT                          0xFFFFFFFE
+#define   S_028814_CULL_BACK(x)                        (((x) & 0x1) << 1)
+#define   G_028814_CULL_BACK(x)                        (((x) >> 1) & 0x1)
+#define   C_028814_CULL_BACK                           0xFFFFFFFD
+#define   S_028814_FACE(x)                             (((x) & 0x1) << 2)
+#define   G_028814_FACE(x)                             (((x) >> 2) & 0x1)
+#define   C_028814_FACE                                0xFFFFFFFB
+#define   S_028814_POLY_MODE(x)                        (((x) & 0x3) << 3)
+#define   G_028814_POLY_MODE(x)                        (((x) >> 3) & 0x3)
+#define   C_028814_POLY_MODE                           0xFFFFFFE7
+#define   S_028814_POLYMODE_FRONT_PTYPE(x)             (((x) & 0x7) << 5)
+#define   G_028814_POLYMODE_FRONT_PTYPE(x)             (((x) >> 5) & 0x7)
+#define   C_028814_POLYMODE_FRONT_PTYPE                0xFFFFFF1F
+#define   S_028814_POLYMODE_BACK_PTYPE(x)              (((x) & 0x7) << 8)
+#define   G_028814_POLYMODE_BACK_PTYPE(x)              (((x) >> 8) & 0x7)
+#define   C_028814_POLYMODE_BACK_PTYPE                 0xFFFFF8FF
+#define   S_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) & 0x1) << 11)
+#define   G_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) >> 11) & 0x1)
+#define   C_028814_POLY_OFFSET_FRONT_ENABLE            0xFFFFF7FF
+#define   S_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) & 0x1) << 12)
+#define   G_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) >> 12) & 0x1)
+#define   C_028814_POLY_OFFSET_BACK_ENABLE             0xFFFFEFFF
+#define   S_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) & 0x1) << 13)
+#define   G_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) >> 13) & 0x1)
+#define   C_028814_POLY_OFFSET_PARA_ENABLE             0xFFFFDFFF
+#define   S_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) & 0x1) << 16)
+#define   G_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) >> 16) & 0x1)
+#define   C_028814_VTX_WINDOW_OFFSET_ENABLE            0xFFFEFFFF
+#define   S_028814_PROVOKING_VTX_LAST(x)               (((x) & 0x1) << 19)
+#define   G_028814_PROVOKING_VTX_LAST(x)               (((x) >> 19) & 0x1)
+#define   C_028814_PROVOKING_VTX_LAST                  0xFFF7FFFF
+#define   S_028814_PERSP_CORR_DIS(x)                   (((x) & 0x1) << 20)
+#define   G_028814_PERSP_CORR_DIS(x)                   (((x) >> 20) & 0x1)
+#define   C_028814_PERSP_CORR_DIS                      0xFFEFFFFF
+#define   S_028814_MULTI_PRIM_IB_ENA(x)                (((x) & 0x1) << 21)
+#define   G_028814_MULTI_PRIM_IB_ENA(x)                (((x) >> 21) & 0x1)
+#define   C_028814_MULTI_PRIM_IB_ENA                   0xFFDFFFFF
+
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define   S_028004_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028004_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028004_SLICE_START                         0xFFFFF800
+#define   S_028004_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028004_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028004_SLICE_MAX                           0xFF001FFF
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define   S_028D24_HTILE_WIDTH(x)                      (((x) & 0x1) << 0)
+#define   G_028D24_HTILE_WIDTH(x)                      (((x) >> 0) & 0x1)
+#define   C_028D24_HTILE_WIDTH                         0xFFFFFFFE
+#define   S_028D24_HTILE_HEIGHT(x)                     (((x) & 0x1) << 1)
+#define   G_028D24_HTILE_HEIGHT(x)                     (((x) >> 1) & 0x1)
+#define   C_028D24_HTILE_HEIGHT                        0xFFFFFFFD
+#define   S_028D24_LINEAR(x)                           (((x) & 0x1) << 2)
+#define   G_028D24_LINEAR(x)                           (((x) >> 2) & 0x1)
+#define   C_028D24_LINEAR                              0xFFFFFFFB
+#define   S_028D24_FULL_CACHE(x)                       (((x) & 0x1) << 3)
+#define   G_028D24_FULL_CACHE(x)                       (((x) >> 3) & 0x1)
+#define   C_028D24_FULL_CACHE                          0xFFFFFFF7
+#define   S_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) & 0x1) << 4)
+#define   G_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) >> 4) & 0x1)
+#define   C_028D24_HTILE_USES_PRELOAD_WIN              0xFFFFFFEF
+#define   S_028D24_PRELOAD(x)                          (((x) & 0x1) << 5)
+#define   G_028D24_PRELOAD(x)                          (((x) >> 5) & 0x1)
+#define   C_028D24_PRELOAD                             0xFFFFFFDF
+#define   S_028D24_PREFETCH_WIDTH(x)                   (((x) & 0x3F) << 6)
+#define   G_028D24_PREFETCH_WIDTH(x)                   (((x) >> 6) & 0x3F)
+#define   C_028D24_PREFETCH_WIDTH                      0xFFFFF03F
+#define   S_028D24_PREFETCH_HEIGHT(x)                  (((x) & 0x3F) << 12)
+#define   G_028D24_PREFETCH_HEIGHT(x)                  (((x) >> 12) & 0x3F)
+#define   C_028D24_PREFETCH_HEIGHT                     0xFFFC0FFF
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define   S_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) & 0x3FF) << 0)
+#define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
+#define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
+#define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define   S_028D0C_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
+#define   S_028D0C_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
+#define   S_028D0C_R700_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 15)
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define   V_028D10_FORCE_OFF                         0
+#define   V_028D10_FORCE_ENABLE                      1
+#define   V_028D10_FORCE_DISABLE                     2
+#define   S_028D10_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
+#define   G_028D10_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
+#define   C_028D10_FORCE_HIZ_ENABLE                    0xFFFFFFFC
+#define   S_028D10_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
+#define   G_028D10_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE0                   0xFFFFFFF3
+#define   S_028D10_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
+#define   G_028D10_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE1                   0xFFFFFFCF
+#define   S_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
+#define   G_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
+#define   C_028D10_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
+#define   S_028D10_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
+#define   G_028D10_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
+#define   C_028D10_FAST_Z_DISABLE                      0xFFFFFF7F
+#define   S_028D10_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
+#define   G_028D10_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
+#define   C_028D10_FAST_STENCIL_DISABLE                0xFFFFFEFF
+#define   S_028D10_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
+#define   G_028D10_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
+#define   C_028D10_NOOP_CULL_DISABLE                   0xFFFFFDFF
+#define   S_028D10_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
+#define   G_028D10_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
+#define   C_028D10_FORCE_COLOR_KILL                    0xFFFFFBFF
+#define   S_028D10_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
+#define   G_028D10_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
+#define   C_028D10_FORCE_Z_READ                        0xFFFFF7FF
+#define   S_028D10_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
+#define   G_028D10_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
+#define   C_028D10_FORCE_STENCIL_READ                  0xFFFFEFFF
+#define   S_028D10_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
+#define   G_028D10_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
+#define   C_028D10_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
+#define   S_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
+#define   G_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
+#define   C_028D10_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
+#define   S_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
+#define   G_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
+#define   C_028D10_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
+#define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
+#define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
+#define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
+#define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
+#define   C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
+#define   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
+#define   G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
+#define   C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define   S_028E00_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E00_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E00_SCALE                               0x00000000
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define   S_028E04_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E04_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E04_OFFSET                              0x00000000
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define   S_028E08_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E08_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E08_SCALE                               0x00000000
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E0C_OFFSET                              0x00000000
+#define R_028A00_PA_SU_POINT_SIZE                    0x028A00
+#define   S_028A00_HEIGHT(x)                           (((x) & 0xFFFF) << 0)
+#define   G_028A00_HEIGHT(x)                           (((x) >> 0) & 0xFFFF)
+#define   C_028A00_HEIGHT                              0xFFFF0000
+#define   S_028A00_WIDTH(x)                            (((x) & 0xFFFF) << 16)
+#define   G_028A00_WIDTH(x)                            (((x) >> 16) & 0xFFFF)
+#define   C_028A00_WIDTH                               0x0000FFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+
+/* diff */
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define   S_0286CC_NUM_INTERP(x)                       (((x) & 0x3F) << 0)
+#define   G_0286CC_NUM_INTERP(x)                       (((x) >> 0) & 0x3F)
+#define   C_0286CC_NUM_INTERP                          0xFFFFFFC0
+#define   S_0286CC_POSITION_ENA(x)                     (((x) & 0x1) << 8)
+#define   G_0286CC_POSITION_ENA(x)                     (((x) >> 8) & 0x1)
+#define   C_0286CC_POSITION_ENA                        0xFFFFFEFF
+#define   S_0286CC_POSITION_CENTROID(x)                (((x) & 0x1) << 9)
+#define   G_0286CC_POSITION_CENTROID(x)                (((x) >> 9) & 0x1)
+#define   C_0286CC_POSITION_CENTROID                   0xFFFFFDFF
+#define   S_0286CC_POSITION_ADDR(x)                    (((x) & 0x1F) << 10)
+#define   G_0286CC_POSITION_ADDR(x)                    (((x) >> 10) & 0x1F)
+#define   C_0286CC_POSITION_ADDR                       0xFFFF83FF
+#define   S_0286CC_PARAM_GEN(x)                        (((x) & 0xF) << 15)
+#define   G_0286CC_PARAM_GEN(x)                        (((x) >> 15) & 0xF)
+#define   C_0286CC_PARAM_GEN                           0xFFF87FFF
+#define   S_0286CC_PERSP_GRADIENT_ENA(x)               (((x) & 0x1) << 28)
+#define   G_0286CC_PERSP_GRADIENT_ENA(x)               (((x) >> 28) & 0x1)
+#define   C_0286CC_PERSP_GRADIENT_ENA                  0xEFFFFFFF
+#define   S_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) & 0x1) << 29)
+#define   G_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) >> 29) & 0x1)
+#define   C_0286CC_LINEAR_GRADIENT_ENA                 0xDFFFFFFF
+#define   S_0286CC_POSITION_SAMPLE(x)                  (((x) & 0x1) << 30)
+#define   G_0286CC_POSITION_SAMPLE(x)                  (((x) >> 30) & 0x1)
+#define   C_0286CC_POSITION_SAMPLE                     0xBFFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define   S_0286D0_FRONT_FACE_ENA(x)                   (((x) & 0x1) << 8)
+#define   G_0286D0_FRONT_FACE_ENA(x)                   (((x) >> 8) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                      0xFFFFFEFF
+#define   S_0286D0_FRONT_FACE_CHAN(x)                  (((x) & 0x3) << 9)
+#define   G_0286D0_FRONT_FACE_CHAN(x)                  (((x) >> 9) & 0x3)
+#define   C_0286D0_FRONT_FACE_CHAN                     0xFFFFF9FF
+#define   S_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) & 0x1) << 11)
+#define   G_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) >> 11) & 0x1)
+#define   C_0286D0_FRONT_FACE_ALL_BITS                 0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ADDR(x)                  (((x) & 0x1F) << 12)
+#define   G_0286D0_FRONT_FACE_ADDR(x)                  (((x) >> 12) & 0x1F)
+#define   C_0286D0_FRONT_FACE_ADDR                     0xFFFE0FFF
+#define   S_0286D0_FOG_ADDR(x)                         (((x) & 0x7F) << 17)
+#define   G_0286D0_FOG_ADDR(x)                         (((x) >> 17) & 0x7F)
+#define   C_0286D0_FOG_ADDR                            0xFF01FFFF
+#define   S_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) & 0x1) << 24)
+#define   G_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) >> 24) & 0x1)
+#define   C_0286D0_FIXED_PT_POSITION_ENA               0xFEFFFFFF
+#define   S_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) & 0x1F) << 25)
+#define   G_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) >> 25) & 0x1F)
+#define   C_0286D0_FIXED_PT_POSITION_ADDR              0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG                   0x0286C4
+#define   S_0286C4_VS_PER_COMPONENT(x)                 (((x) & 0x1) << 0)
+#define   G_0286C4_VS_PER_COMPONENT(x)                 (((x) >> 0) & 0x1)
+#define   C_0286C4_VS_PER_COMPONENT                    0xFFFFFFFE
+#define   S_0286C4_VS_EXPORT_COUNT(x)                  (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                  (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                     0xFFFFFFC1
+#define   S_0286C4_VS_EXPORTS_FOG(x)                   (((x) & 0x1) << 8)
+#define   G_0286C4_VS_EXPORTS_FOG(x)                   (((x) >> 8) & 0x1)
+#define   C_0286C4_VS_EXPORTS_FOG                      0xFFFFFEFF
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) & 0x1F) << 9)
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) >> 9) & 0x1F)
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                 0xFFFFC1FF
+
+#define R_0286E0_SPI_BARYC_CNTL                     0x0286E0
+#define   S_0286E0_PERSP_CENTER_ENA(x)                (((x) & 0x3) << 0)
+#define   G_0286E0_PERSP_CENTER_ENA(x)                (((x) >> 0) & 0x3)
+#define   C_0286E0_PERSP_CENTER_ENA                   0xFFFFFFFC
+#define   S_0286E0_PERSP_CENTROID_ENA(x)              (((x) & 0x3) << 4)
+#define   G_0286E0_PERSP_CENTROID_ENA(x)              (((x) >> 4) & 0x3)
+#define   C_0286E0_PERSP_CENTROID_ENA                 0xFFFFFFCF
+#define   S_0286E0_PERSP_SAMPLE_ENA(x)                (((x) & 0x3) << 8)
+#define   G_0286E0_PERSP_SAMPLE_ENA(x)                (((x) >> 8) & 0x3)
+#define   C_0286E0_PERSP_SAMPLE_ENA                   0xFFFFFCFF
+#define   S_0286E0_PERSP_PULL_MODEL_ENA(x)            (((x) & 0x3) << 12)
+#define   G_0286E0_PERSP_PULL_MODEL_ENA(x)            (((x) >> 12) & 0x3)
+#define   C_0286E0_PERSP_PULL_MODEL_ENA               0xFFFFCFFF
+#define   S_0286E0_LINEAR_CENTER_ENA(x)               (((x) & 0x3) << 16)
+#define   G_0286E0_LINEAR_CENTER_ENA(x)               (((x) >> 16) & 0x3)
+#define   C_0286E0_LINEAR_CENTER_ENA                  0xFFFCFFFF
+#define   S_0286E0_LINEAR_CENTROID_ENA(x)             (((x) & 0x3) << 20)
+#define   G_0286E0_LINEAR_CENTROID_ENA(x)             (((x) >> 20) & 0x3)
+#define   C_0286E0_LINEAR_CENTROID_ENA                0xFFCFFFFF
+#define   S_0286E0_LINEAR_SAMPLE_ENA(x)               (((x) & 0x3) << 24)
+#define   G_0286E0_LINEAR_SAMPLE_ENA(x)               (((x) >> 24) & 0x3)
+#define   C_0286E0_LINEAR_SAMPLE_ENA                  0xFCFFFFFF
+
+
+/* new - diff */
+#define R_028250_PA_SC_VPORT_SCISSOR_TL                0x028250
+#define   S_028250_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028250_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028250_TL_X                                0xFFFF8000
+#define   S_028250_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028250_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028250_TL_Y                                0x8000FFFF
+#define   S_028250_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028250_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028250_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028254_PA_SC_VPORT_SCISSOR_BR                0x028254
+#define   S_028254_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028254_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028254_BR_X                                0xFFFF8000
+#define   S_028254_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028254_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028254_BR_Y                                0x8000FFFF
+/* diff */
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028240_TL_X                                0xFFFF8000
+#define   S_028240_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028240_TL_Y                                0x8000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028244_BR_X                                0xFFFF8000
+#define   S_028244_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028244_BR_Y                                0x8000FFFF
+/* diff */
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0xFFFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0xFFFF)
+#define   C_028030_TL_X                                0xFFFF0000
+#define   S_028030_TL_Y(x)                             (((x) & 0xFFFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0xFFFF)
+#define   C_028030_TL_Y                                0x0000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0xFFFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0xFFFF)
+#define   C_028034_BR_X                                0xFFFF0000
+#define   S_028034_BR_Y(x)                             (((x) & 0xFFFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0xFFFF)
+#define   C_028034_BR_Y                                0x0000FFFF
+/* diff */
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028204_TL_X                                0xFFFF8000
+#define   S_028204_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028204_TL_Y                                0x8000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028208_BR_X                                0xFFFF8000
+#define   S_028208_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028208_BR_Y                                0x8000FFFF
+
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define   S_0287F0_SOURCE_SELECT(x)                    (((x) & 0x3) << 0)
+#define   G_0287F0_SOURCE_SELECT(x)                    (((x) >> 0) & 0x3)
+#define   C_0287F0_SOURCE_SELECT                       0xFFFFFFFC
+#define   S_0287F0_MAJOR_MODE(x)                       (((x) & 0x3) << 2)
+#define   G_0287F0_MAJOR_MODE(x)                       (((x) >> 2) & 0x3)
+#define   C_0287F0_MAJOR_MODE                          0xFFFFFFF3
+#define   S_0287F0_SPRITE_EN(x)                        (((x) & 0x1) << 4)
+#define   G_0287F0_SPRITE_EN(x)                        (((x) >> 4) & 0x1)
+#define   C_0287F0_SPRITE_EN                           0xFFFFFFEF
+#define   S_0287F0_NOT_EOP(x)                          (((x) & 0x1) << 5)
+#define   G_0287F0_NOT_EOP(x)                          (((x) >> 5) & 0x1)
+#define   C_0287F0_NOT_EOP                             0xFFFFFFDF
+#define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
+#define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+
+#define R_030000_SQ_TEX_RESOURCE_WORD0_0             0x030000
+#define   S_030000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_030000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_030000_DIM                                 0xFFFFFFF8
+#define     V_030000_SQ_TEX_DIM_1D                     0x00000000
+#define     V_030000_SQ_TEX_DIM_2D                     0x00000001
+#define     V_030000_SQ_TEX_DIM_3D                     0x00000002
+#define     V_030000_SQ_TEX_DIM_CUBEMAP                0x00000003
+#define     V_030000_SQ_TEX_DIM_1D_ARRAY               0x00000004
+#define     V_030000_SQ_TEX_DIM_2D_ARRAY               0x00000005
+#define     V_030000_SQ_TEX_DIM_2D_MSAA                0x00000006
+#define     V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA          0x00000007
+#define   S_030000_PITCH(x)                            (((x) & 0xFFF) << 6)
+#define   G_030000_PITCH(x)                            (((x) >> 6) & 0xFFF)
+#define   C_030000_PITCH                               0xFFFC003F
+#define   S_030000_TEX_WIDTH(x)                        (((x) & 0x3FFF) << 18)
+#define   G_030000_TEX_WIDTH(x)                        (((x) >> 18) & 0x3FFF)
+#define   C_030000_TEX_WIDTH                           0x0003FFFF
+#define R_030004_SQ_TEX_RESOURCE_WORD1_0             0x030004
+#define   S_030004_TEX_HEIGHT(x)                       (((x) & 0x3FFF) << 0)
+#define   G_030004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x3FFF)
+#define   C_030004_TEX_HEIGHT                          0xFFFFC000
+#define   S_030004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 14)
+#define   G_030004_TEX_DEPTH(x)                        (((x) >> 14) & 0x1FFF)
+#define   C_030004_TEX_DEPTH                           0xF8003FFF
+#define   S_030004_ARRAY_MODE(x)                       (((x) & 0xF) << 28)
+#define   G_030004_ARRAY_MODE(x)                       (((x) >> 28) & 0xF)
+#define   C_030004_ARRAY_MODE                          0x0FFFFFFF
+#define R_030008_SQ_TEX_RESOURCE_WORD2_0             0x030008
+#define   S_030008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_030008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030008_BASE_ADDRESS                        0x00000000
+#define R_03000C_SQ_TEX_RESOURCE_WORD3_0             0x03000C
+#define   S_03000C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03000C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03000C_MIP_ADDRESS                         0x00000000
+#define R_030010_SQ_TEX_RESOURCE_WORD4_0             0x030010
+#define   S_030010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_030010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_030010_FORMAT_COMP_X                       0xFFFFFFFC
+#define     V_030010_SQ_FORMAT_COMP_UNSIGNED           0x00000000
+#define     V_030010_SQ_FORMAT_COMP_SIGNED             0x00000001
+#define     V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED    0x00000002
+#define   S_030010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_030010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_030010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_030010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_030010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_030010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_030010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_030010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_030010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_030010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_030010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_030010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define     V_030010_SQ_NUM_FORMAT_NORM                0x00000000
+#define     V_030010_SQ_NUM_FORMAT_INT                 0x00000001
+#define     V_030010_SQ_NUM_FORMAT_SCALED              0x00000002
+#define   S_030010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_030010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_030010_SRF_MODE_ALL                        0xFFFFFBFF
+#define     V_030010_SFR_MODE_ZERO_CLAMP_MINUS_ONE     0x00000000
+#define     V_030010_SFR_MODE_NO_ZERO                  0x00000001
+#define   S_030010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_030010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_030010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_030010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_030010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_030010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_030010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_030010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_030010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_030010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_030010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_030010_DST_SEL_X                           0xFFF8FFFF
+#define     V_030010_SQ_SEL_X                          0x00000000
+#define     V_030010_SQ_SEL_Y                          0x00000001
+#define     V_030010_SQ_SEL_Z                          0x00000002
+#define     V_030010_SQ_SEL_W                          0x00000003
+#define     V_030010_SQ_SEL_0                          0x00000004
+#define     V_030010_SQ_SEL_1                          0x00000005
+#define   S_030010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_030010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_030010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_030010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_030010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_030010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_030010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_030010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_030010_DST_SEL_W                           0xF1FFFFFF
+#define   S_030010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_030010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_030010_BASE_LEVEL                          0x0FFFFFFF
+#define R_030014_SQ_TEX_RESOURCE_WORD5_0             0x030014
+#define   S_030014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_030014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_030014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_030014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_030014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_030014_BASE_ARRAY                          0xFFFE000F
+#define   S_030014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_030014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_030014_LAST_ARRAY                          0xC001FFFF
+#define R_030018_SQ_TEX_RESOURCE_WORD6_0             0x030018
+#define   S_030018_PERF_MODULATION(x)                  (((x) & 0x7) << 3)
+#define   G_030018_PERF_MODULATION(x)                  (((x) >> 3) & 0x7)
+#define   C_030018_PERF_MODULATION                     0xFFFFFFC7
+#define   S_030018_INTERLACED(x)                       (((x) & 0x1) << 6)
+#define   G_030018_INTERLACED(x)                       (((x) >> 6) & 0x1)
+#define   C_030018_INTERLACED                          0xFFFFFFBF
+#define R_03001C_SQ_TEX_RESOURCE_WORD7_0             0x03001C
+#define   S_03001C_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_03001C_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_03001C_TYPE                                0x3FFFFFFF
+#define     V_03001C_SQ_TEX_VTX_INVALID_TEXTURE        0x00000000
+#define     V_03001C_SQ_TEX_VTX_INVALID_BUFFER         0x00000001
+#define     V_03001C_SQ_TEX_VTX_VALID_TEXTURE          0x00000002
+#define     V_03001C_SQ_TEX_VTX_VALID_BUFFER           0x00000003
+#define   S_03001C_DATA_FORMAT(x)                      (((x) & 0x3F) << 0)
+#define   G_03001C_DATA_FORMAT(x)                      (((x) >> 0) & 0x3F)
+#define   C_03001C_DATA_FORMAT                         0xFFFFFFC0
+
+#define R_030008_SQ_VTX_CONSTANT_WORD2_0             0x030008
+#define   S_030008_BASE_ADDRESS_HI(x)                  (((x) & 0xFF) << 0)
+#define   G_030008_BASE_ADDRESS_HI(x)                  (((x) >> 0) & 0xFF)
+#define   C_030008_BASE_ADDRESS_HI                     0xFFFFFF00
+#define   S_030008_STRIDE(x)                           (((x) & 0x7FF) << 8)
+#define   G_030008_STRIDE(x)                           (((x) >> 8) & 0x7FF)
+#define   C_030008_STRIDE                              0xFFF800FF
+#define   S_030008_CLAMP_X(x)                          (((x) & 0x1) << 19)
+#define   G_030008_CLAMP_X(x)                          (((x) >> 19) & 0x1)
+#define   C_030008_CLAMP_X                             0xFFF7FFFF
+#define   S_030008_DATA_FORMAT(x)                      (((x) & 0x3F) << 20)
+#define   G_030008_DATA_FORMAT(x)                      (((x) >> 20) & 0x3F)
+#define   C_030008_DATA_FORMAT                         0xFC0FFFFF
+#define     V_030008_COLOR_INVALID                     0x00000000
+#define     V_030008_COLOR_8                           0x00000001
+#define     V_030008_COLOR_4_4                         0x00000002
+#define     V_030008_COLOR_3_3_2                       0x00000003
+#define     V_030008_COLOR_16                          0x00000005
+#define     V_030008_COLOR_16_FLOAT                    0x00000006
+#define     V_030008_COLOR_8_8                         0x00000007
+#define     V_030008_COLOR_5_6_5                       0x00000008
+#define     V_030008_COLOR_6_5_5                       0x00000009
+#define     V_030008_COLOR_1_5_5_5                     0x0000000A
+#define     V_030008_COLOR_4_4_4_4                     0x0000000B
+#define     V_030008_COLOR_5_5_5_1                     0x0000000C
+#define     V_030008_COLOR_32                          0x0000000D
+#define     V_030008_COLOR_32_FLOAT                    0x0000000E
+#define     V_030008_COLOR_16_16                       0x0000000F
+#define     V_030008_COLOR_16_16_FLOAT                 0x00000010
+#define     V_030008_COLOR_8_24                        0x00000011
+#define     V_030008_COLOR_8_24_FLOAT                  0x00000012
+#define     V_030008_COLOR_24_8                        0x00000013
+#define     V_030008_COLOR_24_8_FLOAT                  0x00000014
+#define     V_030008_COLOR_10_11_11                    0x00000015
+#define     V_030008_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_030008_COLOR_11_11_10                    0x00000017
+#define     V_030008_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_030008_COLOR_2_10_10_10                  0x00000019
+#define     V_030008_COLOR_8_8_8_8                     0x0000001A
+#define     V_030008_COLOR_10_10_10_2                  0x0000001B
+#define     V_030008_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_030008_COLOR_32_32                       0x0000001D
+#define     V_030008_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_030008_COLOR_16_16_16_16                 0x0000001F
+#define     V_030008_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_030008_COLOR_32_32_32_32                 0x00000022
+#define     V_030008_COLOR_32_32_32_32_FLOAT           0x00000023
+#define   S_030008_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 26)
+#define   G_030008_NUM_FORMAT_ALL(x)                   (((x) >> 26) & 0x3)
+#define   C_030008_NUM_FORMAT_ALL                      0xF3FFFFFF
+#define   S_030008_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 28)
+#define   G_030008_FORMAT_COMP_ALL(x)                  (((x) >> 28) & 0x1)
+#define   C_030008_FORMAT_COMP_ALL                     0xEFFFFFFF
+#define   S_030008_SRF_MODE_ALL(x)                     (((x) & 0x1) << 29)
+#define   G_030008_SRF_MODE_ALL(x)                     (((x) >> 29) & 0x1)
+#define   C_030008_SRF_MODE_ALL                        0xDFFFFFFF
+#define   S_030008_ENDIAN_SWAP(x)                      (((x) & 0x3) << 30)
+#define   G_030008_ENDIAN_SWAP(x)                      (((x) >> 30) & 0x3)
+#define   C_030008_ENDIAN_SWAP                         0x3FFFFFFF
+
+#define R_03000C_SQ_VTX_CONSTANT_WORD3_0             0x03000C
+#define   S_03000C_DST_SEL_X(x)                        (((x) & 0x7) << 3)
+#define   G_03000C_DST_SEL_X(x)                        (((x) >> 3) & 0x7)
+#define     V_03000C_SQ_SEL_X                          0x00000000
+#define     V_03000C_SQ_SEL_Y                          0x00000001
+#define     V_03000C_SQ_SEL_Z                          0x00000002
+#define     V_03000C_SQ_SEL_W                          0x00000003
+#define     V_03000C_SQ_SEL_0                          0x00000004
+#define     V_03000C_SQ_SEL_1                          0x00000005
+#define   S_03000C_DST_SEL_Y(x)                        (((x) & 0x7) << 6)
+#define   G_03000C_DST_SEL_Y(x)                        (((x) >> 6) & 0x7)
+#define   S_03000C_DST_SEL_Z(x)                        (((x) & 0x7) << 9)
+#define   G_03000C_DST_SEL_Z(x)                        (((x) >> 9) & 0x7)
+#define   S_03000C_DST_SEL_W(x)                        (((x) & 0x7) << 12)
+#define   G_03000C_DST_SEL_W(x)                        (((x) >> 12) & 0x7)
+
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define     V_03C000_SQ_TEX_WRAP                       0x00000000
+#define     V_03C000_SQ_TEX_MIRROR                     0x00000001
+#define     V_03C000_SQ_TEX_CLAMP_LAST_TEXEL           0x00000002
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL     0x00000003
+#define     V_03C000_SQ_TEX_CLAMP_HALF_BORDER          0x00000004
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER    0x00000005
+#define     V_03C000_SQ_TEX_CLAMP_BORDER               0x00000006
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_BORDER         0x00000007
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x3) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x3)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF9FF
+#define     V_03C000_SQ_TEX_XY_FILTER_POINT            0x00000000
+#define     V_03C000_SQ_TEX_XY_FILTER_BILINEAR         0x00000001
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x3) << 11)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 11) & 0x3)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFFE7FF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 13)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 13) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFF9FFF
+#define     V_03C000_SQ_TEX_Z_FILTER_NONE              0x00000000
+#define     V_03C000_SQ_TEX_Z_FILTER_POINT             0x00000001
+#define     V_03C000_SQ_TEX_Z_FILTER_LINEAR            0x00000002
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 15)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 15) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFFE7FFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 20)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 20) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFFCFFFFF
+#define     V_03C000_SQ_TEX_BORDER_COLOR_TRANS_BLACK   0x00000000
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK  0x00000001
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE  0x00000002
+#define     V_03C000_SQ_TEX_BORDER_COLOR_REGISTER      0x00000003
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 22)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 22) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xFE3FFFFF
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER        0x00000000
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESS         0x00000001
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL        0x00000002
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL    0x00000003
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER      0x00000004
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL     0x00000005
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x00000006
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS       0x00000007
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 25)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 25) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0xF9FFFFFF
+#define     V_03C000_SQ_TEX_CHROMA_KEY_DISABLE         0x00000000
+#define     V_03C000_SQ_TEX_CHROMA_KEY_KILL            0x00000001
+#define     V_03C000_SQ_TEX_CHROMA_KEY_BLEND           0x00000002
+
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0xFFF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0xFFF)
+#define   C_03C004_MIN_LOD                             0xFFFFF000
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0xFFF) << 12)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 12) & 0xFFF)
+#define   C_03C004_MAX_LOD                             0xFF000FFF
+
+#define   S_03C004_PERF_MIP(x)                         (((x) & 0xF) << 24)
+#define   G_03C004_PERF_MIP(x)                         (((x) >> 24) & 0xF)
+#define   C_03C004_PERF_MIP                            0xF0FFFFFF
+#define   S_03C004_PERF_Z(x)                           (((x) & 0xF) << 28)
+#define   G_03C004_PERF_Z(x)                           (((x) >> 24) & 0xF)
+#define   C_03C004_PERF_Z                              0x0FFFFFFF
+
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS(x)                         (((x) & 0x3FFF) << 0)
+#define   G_03C008_LOD_BIAS(x)                         (((x) >> 0) & 0x3FFF)
+#define   C_03C008_LOD_BIAS                            0xFFFFC000
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0x3F) << 14)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 14) & 0x3F)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFF03FFF
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 20)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 20) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFEFFFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 21)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 21) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFDFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
+
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
+#define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
+#define   C_008958_PRIM_TYPE                           0xFFFFFFC0
+#define     V_008958_DI_PT_NONE                        0x00000000
+#define     V_008958_DI_PT_POINTLIST                   0x00000001
+#define     V_008958_DI_PT_LINELIST                    0x00000002
+#define     V_008958_DI_PT_LINESTRIP                   0x00000003
+#define     V_008958_DI_PT_TRILIST                     0x00000004
+#define     V_008958_DI_PT_TRIFAN                      0x00000005
+#define     V_008958_DI_PT_TRISTRIP                    0x00000006
+#define     V_008958_DI_PT_UNUSED_0                    0x00000007
+#define     V_008958_DI_PT_UNUSED_1                    0x00000008
+#define     V_008958_DI_PT_UNUSED_2                    0x00000009
+#define     V_008958_DI_PT_LINELIST_ADJ                0x0000000A
+#define     V_008958_DI_PT_LINESTRIP_ADJ               0x0000000B
+#define     V_008958_DI_PT_TRILIST_ADJ                 0x0000000C
+#define     V_008958_DI_PT_TRISTRIP_ADJ                0x0000000D
+#define     V_008958_DI_PT_UNUSED_3                    0x0000000E
+#define     V_008958_DI_PT_UNUSED_4                    0x0000000F
+#define     V_008958_DI_PT_TRI_WITH_WFLAGS             0x00000010
+#define     V_008958_DI_PT_RECTLIST                    0x00000011
+#define     V_008958_DI_PT_LINELOOP                    0x00000012
+#define     V_008958_DI_PT_QUADLIST                    0x00000013
+#define     V_008958_DI_PT_QUADSTRIP                   0x00000014
+#define     V_008958_DI_PT_POLYGON                     0x00000015
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V0        0x00000016
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V1        0x00000017
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V2        0x00000018
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V3        0x00000019
+#define     V_008958_DI_PT_2D_FILL_RECT_LIST           0x0000001A
+#define     V_008958_DI_PT_2D_LINE_STRIP               0x0000001B
+#define     V_008958_DI_PT_2D_TRI_STRIP                0x0000001C
+#define R_02881C_PA_CL_VS_OUT_CNTL                   0x02881C
+#define   S_02881C_CLIP_DIST_ENA_0(x)                  (((x) & 0x1) << 0)
+#define   G_02881C_CLIP_DIST_ENA_0(x)                  (((x) >> 0) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_0                     0xFFFFFFFE
+#define   S_02881C_CLIP_DIST_ENA_1(x)                  (((x) & 0x1) << 1)
+#define   G_02881C_CLIP_DIST_ENA_1(x)                  (((x) >> 1) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_1                     0xFFFFFFFD
+#define   S_02881C_CLIP_DIST_ENA_2(x)                  (((x) & 0x1) << 2)
+#define   G_02881C_CLIP_DIST_ENA_2(x)                  (((x) >> 2) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_2                     0xFFFFFFFB
+#define   S_02881C_CLIP_DIST_ENA_3(x)                  (((x) & 0x1) << 3)
+#define   G_02881C_CLIP_DIST_ENA_3(x)                  (((x) >> 3) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_3                     0xFFFFFFF7
+#define   S_02881C_CLIP_DIST_ENA_4(x)                  (((x) & 0x1) << 4)
+#define   G_02881C_CLIP_DIST_ENA_4(x)                  (((x) >> 4) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_4                     0xFFFFFFEF
+#define   S_02881C_CLIP_DIST_ENA_5(x)                  (((x) & 0x1) << 5)
+#define   G_02881C_CLIP_DIST_ENA_5(x)                  (((x) >> 5) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_5                     0xFFFFFFDF
+#define   S_02881C_CLIP_DIST_ENA_6(x)                  (((x) & 0x1) << 6)
+#define   G_02881C_CLIP_DIST_ENA_6(x)                  (((x) >> 6) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_6                     0xFFFFFFBF
+#define   S_02881C_CLIP_DIST_ENA_7(x)                  (((x) & 0x1) << 7)
+#define   G_02881C_CLIP_DIST_ENA_7(x)                  (((x) >> 7) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_7                     0xFFFFFF7F
+#define   S_02881C_CULL_DIST_ENA_0(x)                  (((x) & 0x1) << 8)
+#define   G_02881C_CULL_DIST_ENA_0(x)                  (((x) >> 8) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_0                     0xFFFFFEFF
+#define   S_02881C_CULL_DIST_ENA_1(x)                  (((x) & 0x1) << 9)
+#define   G_02881C_CULL_DIST_ENA_1(x)                  (((x) >> 9) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_1                     0xFFFFFDFF
+#define   S_02881C_CULL_DIST_ENA_2(x)                  (((x) & 0x1) << 10)
+#define   G_02881C_CULL_DIST_ENA_2(x)                  (((x) >> 10) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_2                     0xFFFFFBFF
+#define   S_02881C_CULL_DIST_ENA_3(x)                  (((x) & 0x1) << 11)
+#define   G_02881C_CULL_DIST_ENA_3(x)                  (((x) >> 11) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_3                     0xFFFFF7FF
+#define   S_02881C_CULL_DIST_ENA_4(x)                  (((x) & 0x1) << 12)
+#define   G_02881C_CULL_DIST_ENA_4(x)                  (((x) >> 12) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_4                     0xFFFFEFFF
+#define   S_02881C_CULL_DIST_ENA_5(x)                  (((x) & 0x1) << 13)
+#define   G_02881C_CULL_DIST_ENA_5(x)                  (((x) >> 13) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_5                     0xFFFFDFFF
+#define   S_02881C_CULL_DIST_ENA_6(x)                  (((x) & 0x1) << 14)
+#define   G_02881C_CULL_DIST_ENA_6(x)                  (((x) >> 14) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_6                     0xFFFFBFFF
+#define   S_02881C_CULL_DIST_ENA_7(x)                  (((x) & 0x1) << 15)
+#define   G_02881C_CULL_DIST_ENA_7(x)                  (((x) >> 15) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_7                     0xFFFF7FFF
+#define   S_02881C_USE_VTX_POINT_SIZE(x)               (((x) & 0x1) << 16)
+#define   G_02881C_USE_VTX_POINT_SIZE(x)               (((x) >> 16) & 0x1)
+#define   C_02881C_USE_VTX_POINT_SIZE                  0xFFFEFFFF
+#define   S_02881C_USE_VTX_EDGE_FLAG(x)                (((x) & 0x1) << 17)
+#define   G_02881C_USE_VTX_EDGE_FLAG(x)                (((x) >> 17) & 0x1)
+#define   C_02881C_USE_VTX_EDGE_FLAG                   0xFFFDFFFF
+#define   S_02881C_USE_VTX_RENDER_TARGET_INDX(x)       (((x) & 0x1) << 18)
+#define   G_02881C_USE_VTX_RENDER_TARGET_INDX(x)       (((x) >> 18) & 0x1)
+#define   C_02881C_USE_VTX_RENDER_TARGET_INDX          0xFFFBFFFF
+#define   S_02881C_USE_VTX_VIEWPORT_INDX(x)            (((x) & 0x1) << 19)
+#define   G_02881C_USE_VTX_VIEWPORT_INDX(x)            (((x) >> 19) & 0x1)
+#define   C_02881C_USE_VTX_VIEWPORT_INDX               0xFFF7FFFF
+#define   S_02881C_USE_VTX_KILL_FLAG(x)                (((x) & 0x1) << 20)
+#define   G_02881C_USE_VTX_KILL_FLAG(x)                (((x) >> 20) & 0x1)
+#define   C_02881C_USE_VTX_KILL_FLAG                   0xFFEFFFFF
+#define   S_02881C_VS_OUT_MISC_VEC_ENA(x)              (((x) & 0x1) << 21)
+#define   G_02881C_VS_OUT_MISC_VEC_ENA(x)              (((x) >> 21) & 0x1)
+#define   C_02881C_VS_OUT_MISC_VEC_ENA                 0xFFDFFFFF
+#define   S_02881C_VS_OUT_CCDIST0_VEC_ENA(x)           (((x) & 0x1) << 22)
+#define   G_02881C_VS_OUT_CCDIST0_VEC_ENA(x)           (((x) >> 22) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST0_VEC_ENA              0xFFBFFFFF
+#define   S_02881C_VS_OUT_CCDIST1_VEC_ENA(x)           (((x) & 0x1) << 23)
+#define   G_02881C_VS_OUT_CCDIST1_VEC_ENA(x)           (((x) >> 23) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST1_VEC_ENA              0xFF7FFFFF
+/* diff */
+#define R_028860_SQ_PGM_RESOURCES_VS                 0x028860
+#define   S_028860_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_028860_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_028860_NUM_GPRS                            0xFFFFFF00
+#define   S_028860_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_028860_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_028860_STACK_SIZE                          0xFFFF00FF
+#define   S_028860_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_028860_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_028860_DX10_CLAMP                          0xFFDFFFFF
+#define   S_028860_UNCACHED_FIRST_INST(x)              (((x) & 0x1) << 28)
+#define   G_028860_UNCACHED_FIRST_INST(x)              (((x) >> 28) & 0x1)
+#define   C_028860_UNCACHED_FIRST_INST                 0xEFFFFFFF
+#define R_028864_SQ_PGM_RESOURCES_2_VS               0x028864
+
+#define R_028844_SQ_PGM_RESOURCES_PS                 0x028844
+#define   S_028844_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_028844_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_028844_NUM_GPRS                            0xFFFFFF00
+#define   S_028844_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_028844_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_028844_STACK_SIZE                          0xFFFF00FF
+#define   S_028844_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_028844_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_028844_DX10_CLAMP                          0xFFDFFFFF
+#define   S_028844_PRIME_CACHE_ON_DRAW(x)              (((x) & 0x1) << 23)
+#define   G_028844_PRIME_CACHE_ON_DRAW(x)              (((x) >> 23) & 0x1)
+
+#define   S_028844_UNCACHED_FIRST_INST(x)              (((x) & 0x1) << 28)
+#define   G_028844_UNCACHED_FIRST_INST(x)              (((x) >> 28) & 0x1)
+#define   C_028844_UNCACHED_FIRST_INST                 0xEFFFFFFF
+#define   S_028844_CLAMP_CONSTS(x)                     (((x) & 0x1) << 31)
+#define   G_028844_CLAMP_CONSTS(x)                     (((x) >> 31) & 0x1)
+#define   C_028844_CLAMP_CONSTS                        0x7FFFFFFF
+#define R_028848_SQ_PGM_RESOURCES_2_PS                 0x028848
+
+#define R_028644_SPI_PS_INPUT_CNTL_0                 0x028644
+#define   S_028644_SEMANTIC(x)                         (((x) & 0xFF) << 0)
+#define   G_028644_SEMANTIC(x)                         (((x) >> 0) & 0xFF)
+#define   C_028644_SEMANTIC                            0xFFFFFF00
+#define   S_028644_DEFAULT_VAL(x)                      (((x) & 0x3) << 8)
+#define   G_028644_DEFAULT_VAL(x)                      (((x) >> 8) & 0x3)
+#define   C_028644_DEFAULT_VAL                         0xFFFFFCFF
+#define   S_028644_FLAT_SHADE(x)                       (((x) & 0x1) << 10)
+#define   G_028644_FLAT_SHADE(x)                       (((x) >> 10) & 0x1)
+#define   C_028644_FLAT_SHADE                          0xFFFFFBFF
+#define   S_028644_SEL_CENTROID(x)                     (((x) & 0x1) << 11)
+#define   G_028644_SEL_CENTROID(x)                     (((x) >> 11) & 0x1)
+#define   C_028644_SEL_CENTROID                        0xFFFFF7FF
+#define   S_028644_SEL_LINEAR(x)                       (((x) & 0x1) << 12)
+#define   G_028644_SEL_LINEAR(x)                       (((x) >> 12) & 0x1)
+#define   C_028644_SEL_LINEAR                          0xFFFFEFFF
+#define   S_028644_CYL_WRAP(x)                         (((x) & 0xF) << 13)
+#define   G_028644_CYL_WRAP(x)                         (((x) >> 13) & 0xF)
+#define   C_028644_CYL_WRAP                            0xFFFE1FFF
+#define   S_028644_PT_SPRITE_TEX(x)                    (((x) & 0x1) << 17)
+#define   G_028644_PT_SPRITE_TEX(x)                    (((x) >> 17) & 0x1)
+#define   C_028644_PT_SPRITE_TEX                       0xFFFDFFFF
+#define   S_028644_SEL_SAMPLE(x)                       (((x) & 0x1) << 18)
+#define   G_028644_SEL_SAMPLE(x)                       (((x) >> 18) & 0x1)
+#define   C_028644_SEL_SAMPLE                          0xFFFBFFFF
+#define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
+#define   S_0286D4_FLAT_SHADE_ENA(x)                   (((x) & 0x1) << 0)
+#define   G_0286D4_FLAT_SHADE_ENA(x)                   (((x) >> 0) & 0x1)
+#define   C_0286D4_FLAT_SHADE_ENA                      0xFFFFFFFE
+#define   S_0286D4_PNT_SPRITE_ENA(x)                   (((x) & 0x1) << 1)
+#define   G_0286D4_PNT_SPRITE_ENA(x)                   (((x) >> 1) & 0x1)
+#define   C_0286D4_PNT_SPRITE_ENA                      0xFFFFFFFD
+#define   S_0286D4_PNT_SPRITE_OVRD_X(x)                (((x) & 0x7) << 2)
+#define   G_0286D4_PNT_SPRITE_OVRD_X(x)                (((x) >> 2) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_X                   0xFFFFFFE3
+#define   S_0286D4_PNT_SPRITE_OVRD_Y(x)                (((x) & 0x7) << 5)
+#define   G_0286D4_PNT_SPRITE_OVRD_Y(x)                (((x) >> 5) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_Y                   0xFFFFFF1F
+#define   S_0286D4_PNT_SPRITE_OVRD_Z(x)                (((x) & 0x7) << 8)
+#define   G_0286D4_PNT_SPRITE_OVRD_Z(x)                (((x) >> 8) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_Z                   0xFFFFF8FF
+#define   S_0286D4_PNT_SPRITE_OVRD_W(x)                (((x) & 0x7) << 11)
+#define   G_0286D4_PNT_SPRITE_OVRD_W(x)                (((x) >> 11) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_W                   0xFFFFC7FF
+#define   S_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) & 0x1) << 14)
+#define   G_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) >> 14) & 0x1)
+#define   C_0286D4_PNT_SPRITE_TOP_1                    0xFFFFBFFF
+
+#define SQ_TEX_INST_LD 0x03
+#define SQ_TEX_INST_GET_GRADIENTS_H 0x7
+#define SQ_TEX_INST_GET_GRADIENTS_V 0x8
+
+#define SQ_TEX_INST_SAMPLE 0x10
+#define SQ_TEX_INST_SAMPLE_L 0x11
+#define SQ_TEX_INST_SAMPLE_C 0x18
+#endif
index 0ed177c66bdf09fbf6c5dc23801068348417c142..4664105263a21df46b5253e00cee4ac32c375fa9 100644 (file)
@@ -146,6 +146,13 @@ int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
        case CHIP_RV740:
                bc->chiprev = 1;
                break;
+       case CHIP_CEDAR:
+       case CHIP_REDWOOD:
+       case CHIP_JUNIPER:
+       case CHIP_CYPRESS:
+       case CHIP_HEMLOCK:
+               bc->chiprev = 2;
+               break;
        default:
                R600_ERR("unknown family %d\n", bc->family);
                return -EINVAL;
@@ -345,6 +352,10 @@ static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
        unsigned swizzle_key;
 
+       if (alu->bank_swizzle_force) {
+               alu->bank_swizzle = alu->bank_swizzle_force;
+               return;
+       }
        swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) + 
                (is_const(alu->src[1].sel) ? 2 : 0 ) + 
                (is_const(alu->src[2].sel) ? 1 : 0 );
@@ -357,6 +368,10 @@ static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
        unsigned swizzle_key;
 
+       if (alu->bank_swizzle_force) {
+               alu->bank_swizzle = alu->bank_swizzle_force;
+               return;
+       }
        swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) + 
                (is_const(alu->src[1].sel) ? 2 : 0 ) + 
                (is_const(alu->src[2].sel) ? 1 : 0 );
@@ -462,7 +477,7 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
 
 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 {
-       return r600_bc_add_alu_type(bc, alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU);
+       return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
 }
 
 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
@@ -475,6 +490,7 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
        if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
                return 0;
        }
+       /* all same on EG */
        if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
            bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
            bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
@@ -484,6 +500,7 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
            bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
                return 0;
        }
+       /* same on EG */
        if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
             (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
                LIST_IS_EMPTY(&bc->cf_last->alu)) {
@@ -566,6 +583,7 @@ int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
        return 0;
 }
 
+/* common to all 3 families */
 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
 {
        bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
@@ -583,6 +601,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
        return 0;
 }
 
+/* common to all 3 families */
 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
 {
        bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
@@ -612,6 +631,7 @@ static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsign
        return 0;
 }
 
+/* r600 only, r700/eg bits in r700_asm.c */
 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 {
        unsigned i;
@@ -662,6 +682,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
        return 0;
 }
 
+/* common for r600/r700 - eg in eg_asm.c */
 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 {
        unsigned id = cf->id;
@@ -748,6 +769,8 @@ int r600_bc_build(struct r600_bc *bc)
                        break;
                case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
                case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+               case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+               case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
                        break;
                case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
                case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
@@ -771,7 +794,10 @@ int r600_bc_build(struct r600_bc *bc)
                return -ENOMEM;
        LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
                addr = cf->addr;
-               r = r600_bc_cf_build(bc, cf);
+               if (bc->chiprev == 2)
+                       r = eg_bc_cf_build(bc, cf);
+               else
+                       r = r600_bc_cf_build(bc, cf);
                if (r)
                        return r;
                switch (cf->inst) {
@@ -783,6 +809,7 @@ int r600_bc_build(struct r600_bc *bc)
                                        r = r600_bc_alu_build(bc, alu, addr);
                                        break;
                                case 1:
+                               case 2: /* eg alu is same encoding as r700 */
                                        r = r700_bc_alu_build(bc, alu, addr);
                                        break;
                                default:
@@ -816,6 +843,8 @@ int r600_bc_build(struct r600_bc *bc)
                        break;
                case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
                case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+               case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+               case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
                case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
                case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
                case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
index d4b3463af59ccdceb4b64d71b5e2a4eac96f2808..cc62535e5cd2e332316ca76f25f2a11ee5b1bde0 100644 (file)
@@ -57,6 +57,7 @@ struct r600_bc_alu {
        unsigned                        nliteral;
        unsigned                        literal_added;
        unsigned                        bank_swizzle;
+       unsigned                        bank_swizzle_force;
        u32                             value[4];
        int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
 };
index ed8f2655fba21453a5b0d54691a330861c9d777b..80573a638b7b30453f88f3db3052e8b862aeda8b 100644 (file)
@@ -34,7 +34,6 @@
 #include "r600_resource.h"
 #include "r600d.h"
 
-
 static void r600_destroy_context(struct pipe_context *context)
 {
        struct r600_context *rctx = r600_context(context);
@@ -115,7 +114,10 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
        rctx->screen = rscreen;
        rctx->rw = rscreen->rw;
 
-       rctx->vtbl = &r600_hw_state_vtbl;
+       if (rscreen->chip_class == EVERGREEN)
+               rctx->vtbl = &eg_hw_state_vtbl;
+       else
+               rctx->vtbl = &r600_hw_state_vtbl;
 
        r600_init_blit_functions(rctx);
        r600_init_query_functions(rctx);
index 76a05f81fc568965dbe9284aad719d03f619f7a1..58f6d0232b073146dbfb200b6d90948ff748055c 100644 (file)
@@ -175,6 +175,7 @@ struct r600_context_hw_state_vtbl {
        void (*init_config)(struct r600_context *rctx);
 };
 extern struct r600_context_hw_state_vtbl r600_hw_state_vtbl;
+extern struct r600_context_hw_state_vtbl eg_hw_state_vtbl;
 
 struct r600_context {
        struct pipe_context             context;
@@ -185,6 +186,7 @@ struct r600_context {
        struct radeon_draw              draw;
        struct r600_context_hw_state_vtbl *vtbl;
        struct radeon_state             config;
+       boolean use_mem_constant;
        /* FIXME get rid of those vs_resource,vs/ps_constant */
        struct radeon_state             *vs_resource;
        unsigned                        vs_nresource;
@@ -263,11 +265,16 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 extern void r600_queries_resume(struct pipe_context *ctx);
 extern void r600_queries_suspend(struct pipe_context *ctx);
 
+int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf);
+
 void r600_set_constant_buffer_file(struct pipe_context *ctx,
                                   uint shader, uint index,
                                   struct pipe_resource *buffer);
 void r600_set_constant_buffer_mem(struct pipe_context *ctx,
                                  uint shader, uint index,
                                  struct pipe_resource *buffer);
+void eg_set_constant_buffer(struct pipe_context *ctx,
+                           uint shader, uint index,
+                           struct pipe_resource *buffer);
 
 #endif
index 4de3eae065fc1c1cb3e3bd3b7f0f0ce8ac3ee7a8..3d3e87d7234525befde96a8981eaced3b3a14b8c 100644 (file)
@@ -25,6 +25,7 @@
  *      Jerome Glisse
  *      Dave Airlie
  */
+
 #include <util/u_inlines.h>
 #include <util/u_format.h>
 #include <util/u_memory.h>
index ae3d46e2e51730b6c7fc103789ce2b00a308ca87..0cf9c1c401c6f4279331250bdee17da493857579 100644 (file)
 #define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT             0x00000027
 #define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE        0x00000028
 
-#define BC_INST(bc, x) (x)
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_NOP                             0x00000000
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX                             0x00000001
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX                             0x00000002
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_GDS                             0x00000003
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START                      0x00000004
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END                        0x00000005
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10                 0x00000006
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL                0x00000007
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE                   0x00000008
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK                      0x00000009
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP                            0x0000000A
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_PUSH                            0x0000000B
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_12                                     0x0000000C /* resvd */
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE                            0x0000000D
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_POP                             0x0000000E
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_15                                     0x0000000F
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_16                                     0x00000010
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_17                                     0x00000011
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL                            0x00000012
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS                         0x00000013
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN                          0x00000014
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_EMIT_VERTEX                     0x00000015
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_EMIT_CUT_VERTEX                 0x00000016
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_CUT_VERTEX                      0x00000017
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_KILL                            0x00000018
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_25                                     0x00000019
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_WAIT_ACK                        0x0000001a
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_TC_ACK                          0x0000001b
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_VC_ACK                          0x0000001c
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMPTABLE                       0x0000001d
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_GLOBAL_WAVE_SYNC                0x0000001e
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_HALT                            0x0000001f
 
-#define CTX_INST(x) (x)
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU                         0x00000008
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE             0x00000009
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER               0x0000000A
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER              0x0000000B
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_EXTENDED                    0x0000000C
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE                0x0000000D
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK                   0x0000000E
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER              0x0000000F
+
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD                       0x00000000
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL                       0x00000001
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE                  0x00000002
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX                       0x00000003
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN                       0x00000004
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_DX10                  0x00000005
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_DX10                  0x00000006
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE                      0x00000008
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT                     0x00000009
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE                     0x0000000A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE                     0x0000000B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10                 0x0000000C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10                0x0000000D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10                0x0000000E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10                0x0000000F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT                     0x00000010
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC                     0x00000011
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL                      0x00000012
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE                     0x00000013
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR                     0x00000014
+/* same up to here */
+/*
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA                      0x00000015
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR                0x00000016
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT                  0x00000018
+*/
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT                  0x00000015
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT                  0x00000016
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT                  0x00000017
+/* same again from here */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV                       0x00000019
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP                       0x0000001A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64                    0x0000001B /* new EG */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT64_TO_FLT32            0x0000001C /* new EG */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64            0x0000001D /* new EG */
+/* same */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT           0x0000001E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT           0x0000001F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE                 0x00000020
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT                0x00000021
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE                0x00000022
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE                0x00000023
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV              0x00000024
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP              0x00000025
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR              0x00000026
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE          0x00000027
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH            0x00000028
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH           0x00000029
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH           0x0000002A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH           0x0000002B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE                     0x0000002C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT                    0x0000002D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE                    0x0000002E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE                    0x0000002F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT                   0x00000030
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT                    0x00000031
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT                   0x00000032
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT                   0x00000033
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT                   0x00000034
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT                   0x00000035
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT                   0x00000036
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT                   0x00000037
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT                  0x00000038
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT                  0x00000039
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT                  0x0000003A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT                 0x0000003B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT                 0x0000003C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT                 0x0000003D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT                0x0000003E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT                0x0000003F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT               0x00000040
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT               0x00000041
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT             0x00000042
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT            0x00000043
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT            0x00000044
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT            0x00000045
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT                 0x00000046
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT                0x00000047
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT                0x00000048
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT                0x00000049
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT        0x0000004A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT       0x0000004B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT       0x0000004C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT       0x0000004D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT       0x0000004E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT       0x0000004F
+/* same up to here */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT                0x00000050
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFREV_INT                 0x00000051
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADDC_UINT                 0x00000052
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUBB_UINT                 0x00000053
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_BARRIER             0x00000054
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_SEQ_BEGIN           0x00000055
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_SEQ_END             0x00000056
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_MODE                  0x00000057
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_CF_IDX0               0x00000058
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_CF_IDX1               0x00000059
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_LDS_SIZE              0x0000005A
+
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE                  0x00000081
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED               0x00000082
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE                  0x00000083
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED             0x00000084
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF                  0x00000085
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE                0x00000086
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED         0x00000087
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF              0x00000088
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE            0x00000089
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE                 0x0000008A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN                       0x0000008D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS                       0x0000008E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT                 0x0000008F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT                 0x00000090
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT                0x00000091
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT                0x00000092
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT                 0x00000093
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT                0x00000094
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_64                  0x00000095
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED_64          0x00000096
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_64              0x00000097
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED_64      0x00000098
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_64                   0x00000099
+/* TODO Fill in more ALU */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4                      0x000000BE
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE                 0x000000BF
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE                      0x000000C0
+
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY                      0x000000D6
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW                      0x000000D7
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_X                       0x000000D8
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_Z                       0x000000D9
+
+
+/* TODO ADD OTHER OP3 */
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD                    0x00000014
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M2                 0x00000015
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M4                 0x00000016
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_D2                 0x00000017
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE               0x00000018
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE                      0x00000019
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT                     0x0000001A
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE                     0x0000001B
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT                  0x0000001C
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT                 0x0000001D
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT                 0x0000001E
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT                   0x0000001F
+
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0   0x00000040
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1   0x00000041
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2   0x00000042
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3   0x00000043
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0   0x00000044
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1   0x00000045
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2   0x00000046
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3   0x00000047
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0   0x00000048
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1   0x00000049
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2   0x0000004A
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3   0x0000004B
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0   0x0000004C
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1   0x0000004D
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2   0x0000004E
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3   0x0000004F
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH        0x00000050
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING           0x00000052
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT             0x00000053
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE        0x00000054
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT         0x00000055
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT            0x00000056
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_CACHELESS  0x00000057
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING1          0x00000058
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING2          0x00000059
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING3          0x0000005A
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT_COMBINED 0x0000005B
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS  0x0000005C
+
+#define BC_INST(bc, x) ((bc)->chiprev == 2 ? EG_##x : x)
+
+#define CTX_INST(x) (ctx->bc->chiprev == 2 ? EG_##x : x)
 
 #endif
index 54a61ddfb33072cc5c358c9826a745d6a33c09fe..bb215a33670e08d351740ae7c649c83b82ed0034 100644 (file)
@@ -46,8 +46,10 @@ static const char* r600_get_name(struct pipe_screen* pscreen)
 
        if (family >= CHIP_R600 && family < CHIP_RV770)
                return "R600 (HD2XXX,HD3XXX)";
-       else
+       else if (family < CHIP_CEDAR)
                return "R700 (HD4XXX)";
+       else
+               return "EVERGREEN";
 }
 
 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
@@ -261,6 +263,14 @@ struct pipe_screen *r600_screen_create(struct radeon *rw)
        case CHIP_RV740:
                rscreen->chip_class = R700;
                break;
+       case CHIP_CEDAR:
+       case CHIP_REDWOOD:
+       case CHIP_JUNIPER:
+       case CHIP_CYPRESS:
+       case CHIP_HEMLOCK:
+               rscreen->chip_class = EVERGREEN;
+               rscreen->use_mem_constant = TRUE;
+               break;
        default:
                FREE(rscreen);
                return NULL;
index 129c95ef68a5241de04f10c5988564fb5e26cb88..2a0f7b3056c1b619ea1e80e2320de2f6de581143 100644 (file)
@@ -61,7 +61,7 @@ struct r600_shader_tgsi_instruction {
        int (*process)(struct r600_shader_ctx *ctx);
 };
 
-static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
+static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
 
@@ -242,6 +242,39 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
        return 0;
 }
 
+static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
+{
+       int i, r;
+       struct r600_bc_alu alu;
+
+       for (i = 0; i < 8; i++) {
+               memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+               if (i < 4)
+                       alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
+               else
+                       alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
+
+               if ((i > 1) && (i < 6)) {
+                       alu.dst.sel = ctx->shader->input[gpr].gpr;
+                       alu.dst.write = 1;
+               }
+
+               alu.dst.chan = i % 4;
+               alu.src[0].chan = (1 - (i % 2));
+               alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
+
+               alu.bank_swizzle_force = SQ_ALU_VEC_210;
+               if ((i % 4) == 3)
+                       alu.last = 1;
+               r = r600_bc_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+       return 0;
+}      
+               
+                       
 static int tgsi_declaration(struct r600_shader_ctx *ctx)
 {
        struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
@@ -275,6 +308,10 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
                        if (r)
                                return r;
                }
+               if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
+                       /* turn input into interpolate on EG */
+                       evergreen_interp_alu(ctx, i);
+               }
                break;
        case TGSI_FILE_OUTPUT:
                i = ctx->shader->noutput++;
@@ -391,7 +428,10 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
                        /* reserve first tmp for everyone */
                        r600_get_temp(&ctx);
                        opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
-                       ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
+                       if (ctx.bc->chiprev == 2)
+                               ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
+                       else
+                               ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
                        r = ctx.inst_info->process(&ctx);
                        if (r)
                                goto out_err;
@@ -2161,6 +2201,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
        return tgsi_helper_copy(ctx, inst);
 }
 
+/* r6/7 only for now */
 static int tgsi_arl(struct r600_shader_ctx *ctx)
 {
        /* TODO from r600c, ar values don't persist between clauses */
@@ -2658,3 +2699,161 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_LAST,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 };
+
+static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
+       {TGSI_OPCODE_ARL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_MOV,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
+       {TGSI_OPCODE_LIT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
+       {TGSI_OPCODE_RCP,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
+       {TGSI_OPCODE_RSQ,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
+       {TGSI_OPCODE_EXP,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
+       {TGSI_OPCODE_LOG,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_MUL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
+       {TGSI_OPCODE_ADD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
+       {TGSI_OPCODE_DP3,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+       {TGSI_OPCODE_DP4,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+       {TGSI_OPCODE_DST,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
+       {TGSI_OPCODE_MIN,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
+       {TGSI_OPCODE_MAX,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
+       {TGSI_OPCODE_SLT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
+       {TGSI_OPCODE_SGE,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
+       {TGSI_OPCODE_MAD,       1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
+       {TGSI_OPCODE_SUB,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
+       {TGSI_OPCODE_LRP,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
+       {TGSI_OPCODE_CND,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       /* gap */
+       {20,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_DP2A,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       /* gap */
+       {22,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {23,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_FRC,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
+       {TGSI_OPCODE_CLAMP,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_FLR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
+       {TGSI_OPCODE_ROUND,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_EX2,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
+       {TGSI_OPCODE_LG2,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
+       {TGSI_OPCODE_POW,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
+       {TGSI_OPCODE_XPD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
+       /* gap */
+       {32,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ABS,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
+       {TGSI_OPCODE_RCC,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_DPH,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+       {TGSI_OPCODE_COS,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
+       {TGSI_OPCODE_DDX,       0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
+       {TGSI_OPCODE_DDY,       0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
+       {TGSI_OPCODE_KILP,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* predicated kill */
+       {TGSI_OPCODE_PK2H,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_PK2US,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_PK4B,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_PK4UB,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_RFL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_SEQ,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
+       {TGSI_OPCODE_SFL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_SGT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
+       {TGSI_OPCODE_SIN,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
+       {TGSI_OPCODE_SLE,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
+       {TGSI_OPCODE_SNE,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
+       {TGSI_OPCODE_STR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TEX,       0, SQ_TEX_INST_SAMPLE, tgsi_tex},
+       {TGSI_OPCODE_TXD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TXP,       0, SQ_TEX_INST_SAMPLE, tgsi_tex},
+       {TGSI_OPCODE_UP2H,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UP2US,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UP4B,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UP4UB,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_X2D,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ARA,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ARR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_BRA,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CAL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_RET,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_SSG,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
+       {TGSI_OPCODE_CMP,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
+       {TGSI_OPCODE_SCS,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
+       {TGSI_OPCODE_TXB,       0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
+       {TGSI_OPCODE_NRM,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_DIV,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_DP2,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+       {TGSI_OPCODE_TXL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_BRK,       0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
+       {TGSI_OPCODE_IF,        0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
+       /* gap */
+       {75,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {76,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ELSE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
+       {TGSI_OPCODE_ENDIF,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
+       /* gap */
+       {79,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {80,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_PUSHA,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_POPA,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CEIL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_I2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_NOT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TRUNC,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
+       {TGSI_OPCODE_SHL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       /* gap */
+       {88,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_AND,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_OR,        0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_MOD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_XOR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_SAD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TXF,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TXQ,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CONT,      0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
+       {TGSI_OPCODE_EMIT,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ENDPRIM,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_BGNLOOP,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
+       {TGSI_OPCODE_BGNSUB,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ENDLOOP,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
+       {TGSI_OPCODE_ENDSUB,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       /* gap */
+       {103,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {104,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {105,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {106,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_NOP,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       /* gap */
+       {108,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {109,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {110,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {111,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_NRM4,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CALLNZ,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_IFC,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_BREAKC,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_KIL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* conditional kill */
+       {TGSI_OPCODE_END,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
+       /* gap */
+       {118,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_F2I,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_IDIV,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_IMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_IMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_INEG,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ISGE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ISHR,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ISLT,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_F2U,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_U2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UADD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UDIV,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMAD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMOD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMUL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_USEQ,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_USGE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_USHR,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_USLT,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_USNE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_SWITCH,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CASE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_DEFAULT,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_LAST,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+};
index d0f5726d25180eb9a4ff9d64d6e0bf7b7d992969..0573e63dc8236c613e5eeb904e2c1c20878ea89c 100644 (file)
 #define   S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) & 0x7F) << 23)
 #define   G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) >> 23) & 0x7F)
 #define   C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST                         0xC07FFFFF
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0        0x00000020
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1        0x00000021
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2        0x00000022
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3        0x00000023
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH        0x00000024
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_REDUCTION      0x00000025
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING           0x00000026
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT             0x00000027
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE        0x00000028
+
 #define   S_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x)              (((x) & 0x1) << 30)
 #define   G_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x)              (((x) >> 30) & 0x1)
 #define   C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE                 0xBFFFFFFF
  * 253  SQ_ALU_SRC_LITERAL: literal constant.
  * 254  SQ_ALU_SRC_PV: previous vector result.
  * 255  SQ_ALU_SRC_PS: previous scalar result.
+ * 448  EG - INTERP SRC BASE
  */
 #define     V_SQ_ALU_SRC_0                                           0x000000F8
 #define     V_SQ_ALU_SRC_1                                           0x000000F9
 #define     V_SQ_ALU_SRC_M_1_INT                                     0x000000FB
 #define     V_SQ_ALU_SRC_0_5                                         0x000000FC
 #define     V_SQ_ALU_SRC_LITERAL                                     0x000000FD
+#define     V_SQ_ALU_SRC_PARAM_BASE                                  0x000001C0
 #define   S_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) & 0x1) << 9)
 #define   G_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) >> 9) & 0x1)
 #define   C_SQ_ALU_WORD0_SRC0_REL                                    0xFFFFFDFF
index 28c686a494c92aa25302c4d63f69c991e07ee425..9203f4408c1d17342ddde3ec802f7f80c5d78bbf 100644 (file)
@@ -509,10 +509,14 @@ void r600_init_state_functions(struct r600_context *rctx)
        rctx->context.delete_vs_state = r600_delete_state;
        rctx->context.set_blend_color = r600_set_blend_color;
        rctx->context.set_clip_state = r600_set_clip_state;
-       if (rctx->screen->use_mem_constant)
+
+       if (rctx->screen->chip_class == EVERGREEN)
+               rctx->context.set_constant_buffer = eg_set_constant_buffer;
+       else if (rctx->screen->use_mem_constant)
                rctx->context.set_constant_buffer = r600_set_constant_buffer_mem;
        else
                rctx->context.set_constant_buffer = r600_set_constant_buffer_file;
+
        rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
        rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
        rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
@@ -625,7 +629,6 @@ static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
        struct r600_resource_texture *rtex;
        struct r600_resource *rbuffer;
        struct pipe_surface *surf;
-       int i;
 
        surf = rctx->framebuffer->state.framebuffer.zsbuf;
 
@@ -647,7 +650,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 {
        struct r600_context *rctx = r600_context(ctx);
        unsigned i;
-
+       
        /* build new states */
        rctx->vtbl->rasterizer(rctx, &rctx->hw_states.rasterizer);
        rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor);
@@ -659,12 +662,15 @@ int r600_context_hw_states(struct pipe_context *ctx)
        setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
 
        /* bind states */
+       radeon_draw_bind(&rctx->draw, &rctx->config);
+
        radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
        radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
        radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
        radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
 
-       radeon_draw_bind(&rctx->draw, &rctx->config);
+       radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
+       radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
 
        radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
        radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
index b6698e3885ce0d74c660efb4aeb4487a9f99138c..dec616bce88533d4a37709d8299c658fcdc368c2 100644 (file)
@@ -523,7 +523,7 @@ uint32_t r600_translate_texformat(enum pipe_format format,
                        if (desc->channel[0].size == 5 &&
                            desc->channel[1].size == 6 &&
                            desc->channel[2].size == 5) {
-                               result |= V_0280A0_COLOR_5_6_5;
+                               result = V_0280A0_COLOR_5_6_5;
                                goto out_word4;
                        }
                        goto out_unknown;
@@ -532,14 +532,14 @@ uint32_t r600_translate_texformat(enum pipe_format format,
                            desc->channel[1].size == 5 &&
                            desc->channel[2].size == 5 &&
                            desc->channel[3].size == 1) {
-                               result |= V_0280A0_COLOR_1_5_5_5;
+                               result = V_0280A0_COLOR_1_5_5_5;
                                goto out_word4;
                        }
                        if (desc->channel[0].size == 10 &&
                            desc->channel[1].size == 10 &&
                            desc->channel[2].size == 10 &&
                            desc->channel[3].size == 2) {
-                               result |= V_0280A0_COLOR_10_10_10_2;
+                               result = V_0280A0_COLOR_10_10_10_2;
                                goto out_word4;
                        }
                        goto out_unknown;
@@ -560,36 +560,36 @@ uint32_t r600_translate_texformat(enum pipe_format format,
                case 4:
                        switch (desc->nr_channels) {
                        case 2:
-                               result |= V_0280A0_COLOR_4_4;
+                               result = V_0280A0_COLOR_4_4;
                                goto out_word4;
                        case 4:
-                               result |= V_0280A0_COLOR_4_4_4_4;
+                               result = V_0280A0_COLOR_4_4_4_4;
                                goto out_word4;
                        }
                        goto out_unknown;
                case 8:
                        switch (desc->nr_channels) {
                        case 1:
-                               result |= V_0280A0_COLOR_8;
+                               result = V_0280A0_COLOR_8;
                                goto out_word4;
                        case 2:
-                               result |= V_0280A0_COLOR_8_8;
+                               result = V_0280A0_COLOR_8_8;
                                goto out_word4;
                        case 4:
-                               result |= V_0280A0_COLOR_8_8_8_8;
+                               result = V_0280A0_COLOR_8_8_8_8;
                                goto out_word4;
                        }
                        goto out_unknown;
                case 16:
                        switch (desc->nr_channels) {
                        case 1:
-                               result |= V_0280A0_COLOR_16;
+                               result = V_0280A0_COLOR_16;
                                goto out_word4;
                        case 2:
-                               result |= V_0280A0_COLOR_16_16;
+                               result = V_0280A0_COLOR_16_16;
                                goto out_word4;
                        case 4:
-                               result |= V_0280A0_COLOR_16_16_16_16;
+                               result = V_0280A0_COLOR_16_16_16_16;
                                goto out_word4;
                        }
                }
@@ -600,26 +600,26 @@ uint32_t r600_translate_texformat(enum pipe_format format,
                case 16:
                        switch (desc->nr_channels) {
                        case 1:
-                               result |= V_0280A0_COLOR_16_FLOAT;
+                               result = V_0280A0_COLOR_16_FLOAT;
                                goto out_word4;
                        case 2:
-                               result |= V_0280A0_COLOR_16_16_FLOAT;
+                               result = V_0280A0_COLOR_16_16_FLOAT;
                                goto out_word4;
                        case 4:
-                               result |= V_0280A0_COLOR_16_16_16_16_FLOAT;
+                               result = V_0280A0_COLOR_16_16_16_16_FLOAT;
                                goto out_word4;
                        }
                        goto out_unknown;
                case 32:
                        switch (desc->nr_channels) {
                        case 1:
-                               result |= V_0280A0_COLOR_32_FLOAT;
+                               result = V_0280A0_COLOR_32_FLOAT;
                                goto out_word4;
                        case 2:
-                               result |= V_0280A0_COLOR_32_32_FLOAT;
+                               result = V_0280A0_COLOR_32_32_FLOAT;
                                goto out_word4;
                        case 4:
-                               result |= V_0280A0_COLOR_32_32_32_32_FLOAT;
+                               result = V_0280A0_COLOR_32_32_32_32_FLOAT;
                                goto out_word4;
                        }
                }
index 7f7ce5a4bacfe231c9201c678008c99cc79c2cf1..e754d733afc7283dd1da98a0d41c84e90a82fb0c 100644 (file)
@@ -26,6 +26,7 @@
 #include "r700_sq.h"
 #include <stdio.h>
 
+
 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 {
        unsigned i;
index 5759f363ead9fe1e776701014e131c73f5aeef61..cd063e4a94cd44c40c3927bdf02ee19749e85fb0 100644 (file)
@@ -217,6 +217,7 @@ enum r600_stype {
 };
 
 #include "r600_states_inc.h"
+#include "eg_states_inc.h"
 
 /* R600 QUERY BEGIN/END */
 #define R600_QUERY__OFFSET                     0
diff --git a/src/gallium/winsys/r600/drm/eg_states.h b/src/gallium/winsys/r600/drm/eg_states.h
new file mode 100644 (file)
index 0000000..0334e63
--- /dev/null
@@ -0,0 +1,521 @@
+/*
+ * Copyright Â© 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#ifndef EG_STATES_H
+#define EG_STATES_H
+
+static const struct radeon_register EG_names_CONFIG[] = {
+       {0x00008C00, 0, 0, "SQ_CONFIG"},
+       {0x00009100, 0, 0, "SPI_CONFIG_CNTL"},
+       {0x0000913C, 0, 0, "SPI_CONFIG_CNTL_1"},
+       {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
+       {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
+       {0x00008C0C, 0, 0, "SQ_GPR_RESOURCE_MGMT_3"},
+       {0x00008C18, 0, 0, "SQ_THREAD_RESOURCE_MGMT_1"},
+       {0x00008C1C, 0, 0, "SQ_THREAD_RESOURCE_MGMT_2"},
+       {0x00008C20, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
+       {0x00008C24, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
+       {0x00008C28, 0, 0, "SQ_STACK_RESOURCE_MGMT_3"},
+       {0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
+       {0x00008A14, 0, 0, "PA_CL_ENHANCE"},
+       {0x00028838, 0, 0, "SQ_DYN_GPR_RESOURCE_LIMIT_1"},
+       {0x000288EC, 0, 0, "SQ_LDS_ALLOC_PS"},
+       {0x00028350, 0, 0, "SX_MISC"},
+       {0x00028900, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
+       {0x00028904, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
+       {0x00028908, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
+       {0x0002890C, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
+       {0x00028910, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
+       {0x00028914, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
+       {0x0002891C, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
+       {0x00028920, 0, 0, "SQ_GS_VERT_ITEMSIZE_1"},
+       {0x00028924, 0, 0, "SQ_GS_VERT_ITEMSIZE_2"},
+       {0x00028928, 0, 0, "SQ_GS_VERT_ITEMSIZE_3"},
+       {0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
+       {0x00028A14, 0, 0, "VGT_HOS_CNTL"},
+       {0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
+       {0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
+       {0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
+       {0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
+       {0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
+       {0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
+       {0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
+       {0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
+       {0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
+       {0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
+       {0x00028A40, 0, 0, "VGT_GS_MODE"},
+       {0x00028A48, 0, 0, "PA_SC_MODE_CNTL_0"},
+       {0x00028A4C, 0, 0, "PA_SC_MODE_CNTL_1"},
+       {0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
+       {0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
+       {0x00028B54, 0, 0, "VGT_SHADER_STAGES_EN"},
+       {0x00028B94, 0, 0, "VGT_STRMOUT_CONFIG"},
+       {0x00028B98, 0, 0, "VGT_STRMOUT_BUFFER_CONFIG"},
+};
+
+static const struct radeon_register EG_names_CB_CNTL[] = {
+       {0x00028238, 0, 0, "CB_TARGET_MASK"},
+       {0x0002823C, 0, 0, "CB_SHADER_MASK"},
+       {0x00028808, 0, 0, "CB_COLOR_CONTROL"},
+       {0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
+       {0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
+       {0x00028C3C, 0, 0, "PA_SC_AA_MASK"},
+};
+
+static const struct radeon_register EG_names_RASTERIZER[] = {
+       {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
+       {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
+       {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
+       {0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
+       {0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
+       {0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
+       {0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
+       {0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
+       {0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
+       {0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
+       {0x00028C08, 0, 0, "PA_SU_VTX_CNTL"},
+       {0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
+       {0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
+       {0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
+       {0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
+       {0x00028B78, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
+       {0x00028B7C, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
+       {0x00028B80, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
+       {0x00028B84, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
+       {0x00028B88, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
+       {0x00028B8C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
+};
+
+/* Viewport states are same as r600 */
+static const struct radeon_register EG_names_VIEWPORT[] = {
+       {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
+       {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
+       {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
+       {0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
+       {0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
+       {0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
+       {0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
+       {0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
+       {0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
+};
+
+/* scissor is same as R600 */
+static const struct radeon_register EG_names_SCISSOR[] = {
+       {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
+       {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
+       {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
+       {0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
+       {0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
+       {0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
+       {0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
+       {0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
+       {0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
+       {0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
+       {0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
+       {0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
+       {0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
+       {0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
+       {0x00028230, 0, 0, "PA_SC_EDGERULE"},
+       {0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
+       {0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
+       {0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
+       {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
+       {0x00028234, 0, 0, "PA_SU_HARDWARE_SCREEN_OFFSET"},
+};
+
+/* same as r700 i.e. no blend control */
+static const struct radeon_register EG_names_BLEND[] = {
+       {0x00028414, 0, 0, "CB_BLEND_RED"},
+       {0x00028418, 0, 0, "CB_BLEND_GREEN"},
+       {0x0002841C, 0, 0, "CB_BLEND_BLUE"},
+       {0x00028420, 0, 0, "CB_BLEND_ALPHA"},
+       {0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
+       {0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
+       {0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
+       {0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
+       {0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
+       {0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
+       {0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
+       {0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
+};
+
+/* different */
+static const struct radeon_register EG_names_DSA[] = {
+       {0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
+       {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
+       {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
+       {0x00028430, 0, 0, "DB_STENCILREFMASK"},
+       {0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
+       {0x00028438, 0, 0, "SX_ALPHA_REF"},
+       {0x000286DC, 0, 0, "SPI_FOG_CNTL"},
+       {0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
+       {0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
+       {0x00028000, 0, 0, "DB_RENDER_CONTROL"},
+       {0x0002800C, 0, 0, "DB_RENDER_OVERRIDE"},
+       {0x00028010, 0, 0, "DB_RENDER_OVERRIDE2"},
+       {0x00028AC0, 0, 0, "DB_SRESULTS_COMPARE_STATE0"},
+       {0x00028AC4, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
+       {0x00028AC8, 0, 0, "DB_PRELOAD_CONTROL"},
+       {0x00028B70, 0, 0, "DB_ALPHA_TO_MASK"},
+};
+
+/* different */
+static const struct radeon_register EG_names_VS_SHADER[] = {
+       {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
+       {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
+       {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
+       {0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
+       {0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
+       {0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
+       {0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
+       {0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
+       {0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
+       {0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
+       {0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
+       {0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
+       {0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
+       {0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
+       {0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
+       {0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
+       {0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
+       {0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
+       {0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
+       {0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
+       {0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
+       {0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
+       {0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
+       {0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
+       {0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
+       {0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
+       {0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
+       {0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
+       {0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
+       {0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
+       {0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
+       {0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
+       {0x0002861C, 0, 0, "SPI_VS_OUT_ID_0"}, // all diff belwo
+       {0x00028620, 0, 0, "SPI_VS_OUT_ID_1"},
+       {0x00028624, 0, 0, "SPI_VS_OUT_ID_2"},
+       {0x00028628, 0, 0, "SPI_VS_OUT_ID_3"},
+       {0x0002862C, 0, 0, "SPI_VS_OUT_ID_4"},
+       {0x00028630, 0, 0, "SPI_VS_OUT_ID_5"},
+       {0x00028634, 0, 0, "SPI_VS_OUT_ID_6"},
+       {0x00028638, 0, 0, "SPI_VS_OUT_ID_7"},
+       {0x0002863C, 0, 0, "SPI_VS_OUT_ID_8"},
+       {0x00028640, 0, 0, "SPI_VS_OUT_ID_9"},
+       {0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
+       {0x0002885C, 1, 0, "SQ_PGM_START_VS"}, 
+       {0x00028860, 0, 0, "SQ_PGM_RESOURCES_VS"},
+       {0x00028864, 0, 0, "SQ_PGM_RESOURCES_2_VS"},
+       {0x000288A4, 1, 1, "SQ_PGM_START_FS"},
+       {0x000288A8, 0, 0, "SQ_PGM_RESOURCES_FS"},
+};
+
+static const struct radeon_register EG_names_PS_SHADER[] = {
+       {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
+       {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
+       {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
+       {0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
+       {0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
+       {0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
+       {0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
+       {0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
+       {0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
+       {0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
+       {0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
+       {0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
+       {0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
+       {0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
+       {0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
+       {0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
+       {0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
+       {0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
+       {0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
+       {0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
+       {0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
+       {0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
+       {0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
+       {0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
+       {0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
+       {0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
+       {0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
+       {0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
+       {0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
+       {0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
+       {0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
+       {0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
+       {0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
+       {0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
+       {0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
+       {0x000286D8, 0, 0, "SPI_INPUT_Z"},
+       {0x000286E0, 0, 0, "SPI_BARYC_CNTL"},
+       {0x000286E4, 0, 0, "SPI_PS_IN_CONTROL_2"},
+       {0x000286E8, 0, 0, "SPI_COMPUTE_INPUT_CNTL"},
+       {0x00028840, 1, 0, "SQ_PGM_START_PS"}, // diff
+       {0x00028844, 0, 0, "SQ_PGM_RESOURCES_PS"}, // diff
+       {0x00028848, 0, 0, "SQ_PGM_RESOURCES_2_PS"}, // diff
+       {0x0002884C, 0, 0, "SQ_PGM_EXPORTS_PS"}, // diff
+};
+
+/* different */
+static const struct radeon_register EG_names_UCP[] = {
+       {0x000285BC, 0, 0, "PA_CL_UCP0_X"},
+       {0x000285C0, 0, 0, "PA_CL_UCP0_Y"},
+       {0x000285C4, 0, 0, "PA_CL_UCP0_Z"},
+       {0x000285C8, 0, 0, "PA_CL_UCP0_W"},
+       {0x000285CC, 0, 0, "PA_CL_UCP1_X"},
+       {0x000285D0, 0, 0, "PA_CL_UCP1_Y"},
+       {0x000285D4, 0, 0, "PA_CL_UCP1_Z"},
+       {0x000285D8, 0, 0, "PA_CL_UCP1_W"},
+       {0x000285DC, 0, 0, "PA_CL_UCP2_X"},
+       {0x000285E0, 0, 0, "PA_CL_UCP2_Y"},
+       {0x000285E4, 0, 0, "PA_CL_UCP2_Z"},
+       {0x000285E8, 0, 0, "PA_CL_UCP2_W"},
+       {0x000285EC, 0, 0, "PA_CL_UCP3_X"},
+       {0x000285F0, 0, 0, "PA_CL_UCP3_Y"},
+       {0x000285F4, 0, 0, "PA_CL_UCP3_Z"},
+       {0x000285F8, 0, 0, "PA_CL_UCP3_W"},
+       {0x000285FC, 0, 0, "PA_CL_UCP4_X"},
+       {0x00028600, 0, 0, "PA_CL_UCP4_Y"},
+       {0x00028604, 0, 0, "PA_CL_UCP4_Z"},
+       {0x00028608, 0, 0, "PA_CL_UCP4_W"},
+       {0x0002860C, 0, 0, "PA_CL_UCP5_X"},
+       {0x00028610, 0, 0, "PA_CL_UCP5_Y"},
+       {0x00028614, 0, 0, "PA_CL_UCP5_Z"},
+       {0x0002861C, 0, 0, "PA_CL_UCP5_W"},
+};
+
+static const struct radeon_register EG_names_VS_CBUF[] = {
+       {0x00028180, 0, 0, "ALU_CONST_BUFFER_SIZE_VS_0"},
+       {0x00028980, 1, 0, "ALU_CONST_CACHE_VS_0"},
+};
+
+static const struct radeon_register EG_names_PS_CBUF[] = {
+       {0x00028140, 0, 0, "ALU_CONST_BUFFER_SIZE_PS_0"},
+       {0x00028940, 1, 0, "ALU_CONST_CACHE_PS_0"},
+};
+
+static const struct radeon_register EG_names_PS_RESOURCE[] = {
+       {0x00030000, 0, 0, "RESOURCE0_WORD0"},
+       {0x00030004, 0, 0, "RESOURCE0_WORD1"},
+       {0x00030008, 0, 0, "RESOURCE0_WORD2"},
+       {0x0003000C, 0, 0, "RESOURCE0_WORD3"},
+       {0x00030010, 0, 0, "RESOURCE0_WORD4"},
+       {0x00030014, 0, 0, "RESOURCE0_WORD5"},
+       {0x00030018, 0, 0, "RESOURCE0_WORD6"},
+       {0x0003001c, 0, 0, "RESOURCE0_WORD7"},
+};
+
+static const struct radeon_register EG_names_VS_RESOURCE[] = {
+       {0x00031600, 0, 0, "RESOURCE160_WORD0"},
+       {0x00031604, 0, 0, "RESOURCE160_WORD1"},
+       {0x00031608, 0, 0, "RESOURCE160_WORD2"},
+       {0x0003160C, 0, 0, "RESOURCE160_WORD3"},
+       {0x00031610, 0, 0, "RESOURCE160_WORD4"},
+       {0x00031614, 0, 0, "RESOURCE160_WORD5"},
+       {0x00031618, 0, 0, "RESOURCE160_WORD6"},
+       {0x0003161c, 0, 0, "RESOURCE160_WORD7"},
+};
+
+static const struct radeon_register EG_names_FS_RESOURCE[] = {
+       {0x0003A300, 0, 0, "RESOURCE320_WORD0"},
+       {0x0003A304, 0, 0, "RESOURCE320_WORD1"},
+       {0x0003A308, 0, 0, "RESOURCE320_WORD2"},
+       {0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
+       {0x0003A310, 0, 0, "RESOURCE320_WORD4"},
+       {0x0003A314, 0, 0, "RESOURCE320_WORD5"},
+       {0x0003A318, 0, 0, "RESOURCE320_WORD6"},
+       {0x0003A31C, 0, 0, "RESOURCE320_WORD7"},
+};
+
+static const struct radeon_register EG_names_GS_RESOURCE[] = {
+       {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
+       {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
+       {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
+       {0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
+       {0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
+       {0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
+       {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
+       {0x0003A4DC, 0, 0, "RESOURCE336_WORD7"},
+};
+
+static const struct radeon_register EG_names_PS_SAMPLER[] = {
+       {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
+       {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
+       {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
+};
+
+static const struct radeon_register EG_names_VS_SAMPLER[] = {
+       {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
+       {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
+       {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
+};
+
+static const struct radeon_register EG_names_GS_SAMPLER[] = {
+       {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
+       {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
+       {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
+};
+
+static const struct radeon_register EG_names_PS_SAMPLER_BORDER[] = {
+       {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
+       {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
+       {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
+       {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register EG_names_VS_SAMPLER_BORDER[] = {
+       {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
+       {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
+       {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
+       {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register EG_names_GS_SAMPLER_BORDER[] = {
+       {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
+       {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
+       {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
+       {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register EG_names_CB0[] = {
+       {0x00028C60, 1, 0, "CB_COLOR0_BASE"},
+       {0x00028C64, 0, 0, "CB_COLOR0_PITCH"},
+       {0x00028C68, 0, 0, "CB_COLOR0_SLICE"},
+       {0x00028C6C, 0, 0, "CB_COLOR0_VIEW"},
+       {0x00028C70, 1, 0, "CB_COLOR0_INFO"},
+       {0x00028C74, 0, 0, "CB_COLOR0_ATTRIB"},
+       {0x00028C78, 0, 0, "CB_COLOR0_DIM"},
+};
+
+/* TODO */
+static const struct radeon_register EG_names_CB1[] = {
+       {0x00028044, 1, 0, "CB_COLOR1_BASE"},
+       {0x000280A4, 0, 0, "CB_COLOR1_INFO"},
+       {0x00028064, 0, 0, "CB_COLOR1_SIZE"},
+       {0x00028084, 0, 0, "CB_COLOR1_VIEW"},
+       {0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
+       {0x000280C4, 1, 2, "CB_COLOR1_TILE"},
+       {0x00028104, 0, 0, "CB_COLOR1_MASK"},
+};
+
+static const struct radeon_register EG_names_CB2[] = {
+       {0x00028048, 1, 0, "CB_COLOR2_BASE"},
+       {0x000280A8, 0, 0, "CB_COLOR2_INFO"},
+       {0x00028068, 0, 0, "CB_COLOR2_SIZE"},
+       {0x00028088, 0, 0, "CB_COLOR2_VIEW"},
+       {0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
+       {0x000280C8, 1, 2, "CB_COLOR2_TILE"},
+       {0x00028108, 0, 0, "CB_COLOR2_MASK"},
+};
+
+static const struct radeon_register EG_names_CB3[] = {
+       {0x0002804C, 1, 0, "CB_COLOR3_BASE"},
+       {0x000280AC, 0, 0, "CB_COLOR3_INFO"},
+       {0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
+       {0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
+       {0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
+       {0x000280CC, 1, 2, "CB_COLOR3_TILE"},
+       {0x0002810C, 0, 0, "CB_COLOR3_MASK"},
+};
+
+static const struct radeon_register EG_names_CB4[] = {
+       {0x00028050, 1, 0, "CB_COLOR4_BASE"},
+       {0x000280B0, 0, 0, "CB_COLOR4_INFO"},
+       {0x00028070, 0, 0, "CB_COLOR4_SIZE"},
+       {0x00028090, 0, 0, "CB_COLOR4_VIEW"},
+       {0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
+       {0x000280D0, 1, 2, "CB_COLOR4_TILE"},
+       {0x00028110, 0, 0, "CB_COLOR4_MASK"},
+};
+
+static const struct radeon_register EG_names_CB5[] = {
+       {0x00028054, 1, 0, "CB_COLOR5_BASE"},
+       {0x000280B4, 0, 0, "CB_COLOR5_INFO"},
+       {0x00028074, 0, 0, "CB_COLOR5_SIZE"},
+       {0x00028094, 0, 0, "CB_COLOR5_VIEW"},
+       {0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
+       {0x000280D4, 1, 2, "CB_COLOR5_TILE"},
+       {0x00028114, 0, 0, "CB_COLOR5_MASK"},
+};
+
+static const struct radeon_register EG_names_CB6[] = {
+       {0x00028058, 1, 0, "CB_COLOR6_BASE"},
+       {0x000280B8, 0, 0, "CB_COLOR6_INFO"},
+       {0x00028078, 0, 0, "CB_COLOR6_SIZE"},
+       {0x00028098, 0, 0, "CB_COLOR6_VIEW"},
+       {0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
+       {0x000280D8, 1, 2, "CB_COLOR6_TILE"},
+       {0x00028118, 0, 0, "CB_COLOR6_MASK"},
+};
+
+static const struct radeon_register EG_names_CB7[] = {
+       {0x0002805C, 1, 0, "CB_COLOR7_BASE"},
+       {0x000280BC, 0, 0, "CB_COLOR7_INFO"},
+       {0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
+       {0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
+       {0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
+       {0x000280DC, 1, 2, "CB_COLOR7_TILE"},
+       {0x0002811C, 0, 0, "CB_COLOR7_MASK"},
+};
+/* TODO */
+
+/* different - TODO */
+static const struct radeon_register EG_names_DB[] = {
+       {0x00028014, 1, 0, "DB_HTILE_DATA_BASE"},
+       {0x00028040, 1, 0, "DB_Z_INFO"},
+       {0x00028044, 0, 0, "DB_STENCIL_INFO"},
+       {0x00028058, 0, 0, "DB_DEPTH_SIZE"},
+       {0x0002805C, 0, 0, "DB_DEPTH_SLICE"},
+       {0x00028008, 0, 0, "DB_DEPTH_VIEW"},
+       {0x00028ABC, 0, 0, "DB_HTILE_SURFACE"},
+       {0x00028048, 1, 0, "DB_Z_READ_BASE"},
+       {0x0002804C, 1, 0, "DB_STENCIL_READ_BASE"},
+       {0x00028050, 1, 0, "DB_Z_WRITE_BASE"},
+       {0x00028054, 1, 0, "DB_STENCIL_WRITE_BASE"},
+};
+
+static const struct radeon_register EG_names_VGT[] = {
+       {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, //s
+       {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, //s
+       {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, //s
+       {0x00028408, 0, 0, "VGT_INDX_OFFSET"}, //s
+       {0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, //s
+       {0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, //s
+       {0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, //s
+       {0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, //s
+       {0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, //s
+       {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, //s
+};
+
+static const struct radeon_register EG_names_DRAW[] = { 
+       {0x00008970, 0, 0, "VGT_NUM_INDICES"},
+       {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},    //same
+       {0x000287E8, 1, 0, "VGT_DMA_BASE"},       //same
+       {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, //same
+};
+
+static const struct radeon_register EG_names_VGT_EVENT[] = {
+       {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, //done
+};
+
+static const struct radeon_register EG_names_CB_FLUSH[] = {
+};
+
+static const struct radeon_register EG_names_DB_FLUSH[] = {
+};
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/gen_eg_states.py b/src/gallium/winsys/r600/drm/gen_eg_states.py
new file mode 100644 (file)
index 0000000..b2e5b22
--- /dev/null
@@ -0,0 +1,39 @@
+import os
+import re
+
+def main():
+    fileIN = open('eg_states.h', 'r')
+    line = fileIN.readline()
+    next_is_reg = False
+    count = 0
+
+    print "/* This file is autogenerated from eg_states.h - do not edit directly */"
+    print "/* autogenerating script is gen_eg_states.py */"
+    print ""
+    while line:
+        if line[0:2] == "};":
+            if next_is_reg == True:
+                print "#define " + name + "_SIZE\t\t", count
+                print "#define " + name + "_PM4 128\t\t"
+            next_is_reg = False
+            count = 0
+            print ""
+    
+        if line[0:6] == "static":
+            name = line.rstrip("\n")
+            cline = name.split()
+            name = cline[4].split('[')
+            name = name[0].replace("_names", "")
+            print "/* " + name + " */"
+            next_is_reg = True
+        elif next_is_reg == True:
+            reg = line.split();
+            reg = reg[3].replace("},", "")
+            reg = reg.replace("\"", "")
+            print "#define " + name + "__" + reg + "\t\t", count
+            count = count + 1
+
+        line = fileIN.readline()
+
+if __name__ == "__main__":
+    main()
index 3160beace7e4b7c5bbcd7883713d970b74e0e340..3570ee1485ec81f2be4682c063e02cba52a16a17 100644 (file)
@@ -46,7 +46,10 @@ static int r700_state_pm4_config(struct radeon_state *state);
 static int r600_state_pm4_db_flush(struct radeon_state *state);
 static int r600_state_pm4_cb_flush(struct radeon_state *state);
 
+static int eg_state_pm4_vgt(struct radeon_state *state);
+
 #include "r600_states.h"
+#include "eg_states.h"
 
 
 #define SUB_NONE(param) { { 0, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } }
@@ -55,6 +58,12 @@ static int r600_state_pm4_cb_flush(struct radeon_state *state);
 #define SUB_GS(param) { R600_SHADER_GS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
 #define SUB_FS(param) { R600_SHADER_FS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
 
+#define EG_SUB_NONE(param) { { 0, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } }
+#define EG_SUB_PS(param) { R600_SHADER_PS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+#define EG_SUB_VS(param) { R600_SHADER_VS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+#define EG_SUB_GS(param) { R600_SHADER_GS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+#define EG_SUB_FS(param) { R600_SHADER_FS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+
 /* some of these are overriden at runtime for R700 */
 struct radeon_stype_info r600_stypes[] = {
        { R600_STATE_CONFIG, 1, 0, r600_state_pm4_config, SUB_NONE(CONFIG), },
@@ -89,6 +98,39 @@ struct radeon_stype_info r600_stypes[] = {
 };
 #define STYPES_SIZE Elements(r600_stypes)
 
+struct radeon_stype_info eg_stypes[] = {
+       { R600_STATE_CONFIG, 1, 0, r700_state_pm4_config, EG_SUB_NONE(CONFIG), },
+       { R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB_CNTL) },
+       { R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(RASTERIZER) },
+       { R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(VIEWPORT) },
+       { R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(SCISSOR) },
+       { R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(BLEND), },
+       { R600_STATE_DSA, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DSA), },
+       { R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_SHADER), EG_SUB_VS(VS_SHADER) } },
+       { R600_STATE_CBUF, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_CBUF), EG_SUB_VS(VS_CBUF) } },
+       { R600_STATE_RESOURCE, 176, 0x20, r600_state_pm4_resource, { EG_SUB_PS(PS_RESOURCE), EG_SUB_VS(VS_RESOURCE), EG_SUB_GS(GS_RESOURCE), EG_SUB_FS(FS_RESOURCE)} },
+       { R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER), EG_SUB_VS(VS_SAMPLER), EG_SUB_GS(GS_SAMPLER) } },
+       { R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER_BORDER), EG_SUB_VS(VS_SAMPLER_BORDER), EG_SUB_GS(GS_SAMPLER_BORDER) } },
+       { R600_STATE_CB0, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB0) },
+       { R600_STATE_CB1, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB1) },
+       { R600_STATE_CB2, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB2) },
+       { R600_STATE_CB3, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB3) },
+       { R600_STATE_CB4, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB4) },
+       { R600_STATE_CB5, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB5) },
+       { R600_STATE_CB6, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB6) },
+       { R600_STATE_CB7, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB7) },
+       { R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, EG_SUB_NONE(VGT_EVENT) },
+       { R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, EG_SUB_NONE(VGT_EVENT) },
+       { R600_STATE_DB, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DB) },
+       { R600_STATE_UCP, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(UCP) },
+       { R600_STATE_VGT, 1, 0, eg_state_pm4_vgt, EG_SUB_NONE(VGT) },
+       { R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, EG_SUB_NONE(DRAW) },
+       { R600_STATE_CB_FLUSH, 1, 0, r600_state_pm4_cb_flush, EG_SUB_NONE(CB_FLUSH) },
+       { R600_STATE_DB_FLUSH, 1, 0, r600_state_pm4_db_flush, EG_SUB_NONE(DB_FLUSH) },
+
+};
+#define EG_STYPES_SIZE Elements(eg_stypes)
+
 static const struct radeon_register *get_regs(struct radeon_state *state)
 {
        return state->stype->reginfo[state->shader_index].regs;
@@ -162,6 +204,72 @@ static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset,
        return -EINVAL;
 }
 
+static int eg_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
+{
+       const struct radeon_register *regs = get_regs(state);
+       unsigned i;
+       int r;
+
+       if (!offset) {
+               fprintf(stderr, "%s invalid register for state %d %d\n",
+                       __func__, state->stype->stype, id);
+               return -EINVAL;
+       }
+       if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
+               state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg);
+               state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2;
+               for (i = 0; i < nreg; i++) {
+                       state->pm4[state->cpm4++] = state->states[id + i];
+               }
+               for (i = 0; i < nreg; i++) {
+                       if (regs[id + i].need_reloc) {
+                               state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+                               r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+                               if (r)
+                                       return r;
+                               state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+                       }
+               }
+               return 0;
+       }
+       if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
+               state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg);
+               state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2;
+               for (i = 0; i < nreg; i++) {
+                       state->pm4[state->cpm4++] = state->states[id + i];
+               }
+               for (i = 0; i < nreg; i++) {
+                       if (regs[id + i].need_reloc) {
+                               state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+                               r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+                               if (r)
+                                       return r;
+                               state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+                       }
+               }
+               return 0;
+       }
+       if (offset >= EG_RESOURCE_OFFSET && offset < EG_RESOURCE_END) {
+               state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nreg);
+               state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2;
+               for (i = 0; i < nreg; i++) {
+                       state->pm4[state->cpm4++] = state->states[id + i];
+               }
+               return 0;
+       }
+       if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
+               state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg);
+               state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2;
+               for (i = 0; i < nreg; i++) {
+                       state->pm4[state->cpm4++] = state->states[id + i];
+               }
+               return 0;
+       }
+       fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset);
+       return -EINVAL;
+}
+
+
 static int r600_state_pm4_generic(struct radeon_state *state)
 {
        const struct radeon_register *regs = get_regs(state);
@@ -180,7 +288,10 @@ static int r600_state_pm4_generic(struct radeon_state *state)
                        nreg++;
                        loffset = coffset;
                } else {
-                       r = r600_state_pm4_bytecode(state, offset, start, nreg);
+                       if (state->radeon->family >= CHIP_CEDAR)
+                               r = eg_state_pm4_bytecode(state, offset, start, nreg);
+                       else
+                               r = r600_state_pm4_bytecode(state, offset, start, nreg);
                        if (r) {
                                fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg);
                                return r;
@@ -190,7 +301,11 @@ static int r600_state_pm4_generic(struct radeon_state *state)
                        start = i;
                }
        }
-       return r600_state_pm4_bytecode(state, offset, start, nreg);
+       if (state->radeon->family >= CHIP_CEDAR)
+               r = eg_state_pm4_bytecode(state, offset, start, nreg);
+       else
+               r = r600_state_pm4_bytecode(state, offset, start, nreg);
+       return r;
 }
 
 static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags)
@@ -314,6 +429,28 @@ static int r600_state_pm4_shader(struct radeon_state *state)
        return r600_state_pm4_generic(state);
 }
 
+static int eg_state_pm4_vgt(struct radeon_state *state)
+{
+       int r;
+       r = eg_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, EG_VGT__VGT_MAX_VTX_INDX, 1);
+       if (r)
+               return r;
+       r = eg_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, EG_VGT__VGT_MIN_VTX_INDX, 1);
+       if (r)
+               return r;
+       r = eg_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, EG_VGT__VGT_INDX_OFFSET, 1);
+       if (r)
+               return r;
+       r = eg_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, EG_VGT__VGT_PRIMITIVE_TYPE, 1);
+       if (r)
+               return r;
+       state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0);
+       state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_INDEX_TYPE];
+       state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0);
+       state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_NUM_INSTANCES];
+       return 0;
+}
+
 static int r600_state_pm4_vgt(struct radeon_state *state)
 {
        int r;
@@ -362,6 +499,7 @@ static int r600_state_pm4_draw(struct radeon_state *state)
        }
        state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
        state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+
        return 0;
 }
 
@@ -390,11 +528,15 @@ static int r600_state_pm4_db_flush(struct radeon_state *state)
 static int r600_state_pm4_resource(struct radeon_state *state)
 {
        u32 flags, type, nbo, offset, soffset;
-       int r;
+       int r, nres;
        const struct radeon_register *regs = get_regs(state);
 
        soffset = state->id * state->stype->stride;
-       type = G_038018_TYPE(state->states[6]);
+       if (state->radeon->family >= CHIP_CEDAR)
+               type = G_038018_TYPE(state->states[7]);
+       else
+               type = G_038018_TYPE(state->states[6]);
+
        switch (type) {
        case 2:
                flags = S_0085F0_TC_ACTION_ENA(1);
@@ -413,8 +555,15 @@ static int r600_state_pm4_resource(struct radeon_state *state)
        }
        r600_state_pm4_with_flush(state, flags);
        offset = regs[0].offset + soffset;
-       state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7);
-       state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
+       if (state->radeon->family >= CHIP_CEDAR)
+               nres = 8;
+       else
+               nres = 7;
+       state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nres);
+       if (state->radeon->family >= CHIP_CEDAR)
+               state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2;
+       else
+               state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
        state->pm4[state->cpm4++] = state->states[0];
        state->pm4[state->cpm4++] = state->states[1];
        state->pm4[state->cpm4++] = state->states[2];
@@ -422,6 +571,9 @@ static int r600_state_pm4_resource(struct radeon_state *state)
        state->pm4[state->cpm4++] = state->states[4];
        state->pm4[state->cpm4++] = state->states[5];
        state->pm4[state->cpm4++] = state->states[6];
+       if (state->radeon->family >= CHIP_CEDAR)
+               state->pm4[state->cpm4++] = state->states[7];
+
        state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
        r = radeon_state_reloc(state, state->cpm4, 0);
        if (r)
@@ -469,31 +621,43 @@ static void r600_modify_type_array(struct radeon *radeon)
        }
 }
 
-static void r600_build_types_array(struct radeon *radeon)
+static void build_types_array(struct radeon *radeon, struct radeon_stype_info *types, int size)
 {
        int i, j;
        int id = 0;
 
-       for (i = 0; i < STYPES_SIZE; i++) {
-               r600_stypes[i].base_id = id;
-               r600_stypes[i].npm4 = 128;
-               if (r600_stypes[i].reginfo[0].shader_type == 0) {
-                       id += r600_stypes[i].num;
+       for (i = 0; i < size; i++) {
+               types[i].base_id = id;
+               types[i].npm4 = 128;
+               if (types[i].reginfo[0].shader_type == 0) {
+                       id += types[i].num;
                } else {
                        for (j = 0; j < R600_SHADER_MAX; j++) {
-                               if (r600_stypes[i].reginfo[j].shader_type)
-                                       id += r600_stypes[i].num;
+                               if (types[i].reginfo[j].shader_type)
+                                       id += types[i].num;
                        }
                }
        }
-       radeon->stype = r600_stypes;
-       radeon->nstype = STYPES_SIZE;
+       radeon->stype = types;
+       radeon->nstype = size;
+}
 
+static void r600_build_types_array(struct radeon *radeon)
+{
+       build_types_array(radeon, r600_stypes, STYPES_SIZE);
        r600_modify_type_array(radeon);
 }
 
+static void eg_build_types_array(struct radeon *radeon)
+{
+       build_types_array(radeon, eg_stypes, EG_STYPES_SIZE);
+}
+
 int r600_init(struct radeon *radeon)
 {
-       r600_build_types_array(radeon);
+       if (radeon->family >= CHIP_CEDAR)
+               eg_build_types_array(radeon);
+       else
+               r600_build_types_array(radeon);
        return 0;
 }
index e8c2dc0651c1373506492e32d760aa011c1a7287..05f31571f424fcc1fada9a3e12ab7ea66948f00f 100644 (file)
 #define R600_BOOL_CONST_OFFSET                 0X0003E380
 #define R600_BOOL_CONST_END                    0X00040000
 
+/* evergreen values */
+#define EG_RESOURCE_OFFSET                 0x00030000
+#define EG_RESOURCE_END                    0x00030400
+#define EG_LOOP_CONST_OFFSET               0x0003A200
+#define EG_LOOP_CONST_END                  0x0003A26C
+#define EG_BOOL_CONST_OFFSET               0x0003A500
+#define EG_BOOL_CONST_END                  0x0003A506
+
+
 #define PKT3_NOP                               0x10
 #define PKT3_INDIRECT_BUFFER_END               0x17
 #define PKT3_SET_PREDICATION                   0x20
index e2d813ebac71e270bd6121d3eab7dc8009d51204..64ccc7db87731e7caf38f5d9dc2b13dc7e7d8e27 100644 (file)
@@ -79,6 +79,11 @@ struct radeon *radeon_new(int fd, unsigned device)
        case CHIP_RV730:
        case CHIP_RV710:
        case CHIP_RV740:
+       case CHIP_CEDAR:
+       case CHIP_REDWOOD:
+       case CHIP_JUNIPER:
+       case CHIP_CYPRESS:
+       case CHIP_HEMLOCK:
                if (r600_init(radeon)) {
                        return radeon_decref(radeon);
                }
@@ -110,11 +115,6 @@ struct radeon *radeon_new(int fd, unsigned device)
        case CHIP_RV560:
        case CHIP_RV570:
        case CHIP_R580:
-       case CHIP_CEDAR:
-       case CHIP_REDWOOD:
-       case CHIP_JUNIPER:
-       case CHIP_CYPRESS:
-       case CHIP_HEMLOCK:
        default:
                fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
                        __func__, radeon->device);