Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM"
authorKenneth Graunke <kenneth@whitecape.org>
Mon, 23 Sep 2019 23:30:29 +0000 (16:30 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 23 Sep 2019 23:31:23 +0000 (16:31 -0700)
This reverts commit 729de1488f49033bc181b8123af5658228a51bf1.

It turns out that, although the register is in the logical context,
it isn't whitelisted, so we can't actually write it from userspace
batch buffers.  The write just becomes a noop, which is why we saw
no performance changes.

I manually whitelisted it, and still observed no performance gains, but
it did regress KHR-GL46.texture_cube_map_array.color_depth_attachments
on the iris driver.  So we might need to fix something before enabling
this.  To prevent it randomly getting turned on should the kernel ever
whitelist this register, we revert the patch for now.

src/gallium/drivers/iris/iris_state.c
src/intel/vulkan/genX_state.c
src/mesa/drivers/dri/i965/brw_defines.h
src/mesa/drivers/dri/i965/brw_state_upload.c

index 370dc52df38e1ccd2aa69ed4fbecc36bff2fb846..113e2b4e9a529d864a7541e7297003f06915af30 100644 (file)
@@ -824,15 +824,6 @@ iris_init_render_context(struct iris_screen *screen,
       iris_upload_slice_hashing_state(batch);
 #endif
 
-#if GEN_GEN >= 11
-      /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM */
-      iris_pack_state(GENX(COMMON_SLICE_CHICKEN4), &reg_val, reg) {
-         reg.EnableHardwareFilteringinWM = true;
-         reg.EnableHardwareFilteringinWMMask = true;
-      }
-      iris_emit_lri(batch, COMMON_SLICE_CHICKEN4, reg_val);
-#endif
-
    /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
     * changing it dynamically.  We set it to the maximum size here, and
     * instead include the render target dimensions in the viewport, so
index 06b9d497cb05e679e94d158d62c956b02dbd5d7f..df76b33a7c35a24a5d95e2e933a1269b2954b2a0 100644 (file)
@@ -292,17 +292,6 @@ genX(init_device_state)(struct anv_device *device)
          lri.DataDWord      = cache_mode_0;
       }
    }
-
-   /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM. */
-   uint32_t common_slice_chicken4;
-   anv_pack_struct(&common_slice_chicken4, GENX(COMMON_SLICE_CHICKEN4),
-                   .EnableHardwareFilteringinWM = true,
-                   .EnableHardwareFilteringinWMMask = true);
-
-   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
-      lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN4_num);
-      lri.DataDWord      = common_slice_chicken4;
-   }
 #endif
 
    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
index 5a9e77576ecd13a84a7bf56ae165a8a392002ebc..76ec9a26a27a8f9c1e0a873b5f956edd6cd69303 100644 (file)
@@ -1660,10 +1660,6 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GLK_SCEC_BARRIER_MODE_MASK        REG_MASK(1 << 7)
 # define GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE (1 << 11)
 
-
-#define COMMON_SLICE_CHICKEN4                               0x7300
-# define GEN11_ENABLE_HARDWARE_FILTERING_IN_WM              (1 << 5)
-
 #define HALF_SLICE_CHICKEN7                0xE194
 # define TEXEL_OFFSET_FIX_ENABLE           (1 << 1)
 # define TEXEL_OFFSET_FIX_MASK             REG_MASK(1 << 1)
index dfbcea586cce3cfdf49e2a3796ba026aa4b9aafe..87e459376a80ed33dbb36dff487ed1e019b2327f 100644 (file)
@@ -189,11 +189,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
        */
       brw_load_register_imm32(brw, GEN8_L3CNTLREG,
                               GEN8_L3CNTLREG_EDBC_NO_HANG);
-
-      /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM */
-      brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN4,
-                              GEN11_ENABLE_HARDWARE_FILTERING_IN_WM |
-                              REG_MASK(GEN11_ENABLE_HARDWARE_FILTERING_IN_WM));
    }
 
    /* hardware specification recommends disabling repacking for