test privileged rfid call

diff --git a/src/soc/config/endian.py b/src/soc/config/endian.py
index eb6e0c3f97be5b76b785d318e469c13e96190e9e..0aaa61c25ea4c59f88cfe0ed7c8bfa9cab4cbee8 100644 (file)
--- a/src/soc/config/endian.py
+++ b/src/soc/config/endian.py
@@ -1,5 +1,5 @@
 global bigendian
-bigendian = 0
+bigendian = 1
 
 def set_endian_mode(mode):
     bigendian = mode

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 75d2d48ec119e2511ff06ec8347659d2669028b3..146708ed41fdf03218b7c20f3538b578689df6be 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -143,6 +143,16 @@ class TrapTestCase(FHDLTestCase):
         msr = 1 << MSR.PR # set in "problem state"
         self.run_tst_program(Program(lst, bigendian), initial_regs,
                                                       initial_msr=msr)
+    def test_7_rfid_priv_0(self):
+        lst = ["rfid"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 1
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
+        msr = 1 << MSR.PR # set in "problem state"
+        self.run_tst_program(Program(lst, bigendian),
+                             initial_regs, initial_sprs,
+                             initial_msr=msr)
+
     def test_999_illegal(self):
         # ok, um this is a bit of a cheat: use an instruction we know
         # is not implemented by either ISACaller or the core