rename cell mux to consistent naming scheme

diff --git a/src/actual_pinmux.py b/src/actual_pinmux.py
index ff6902af01399afefb559eb409c52687d0397d34..99db5a05a14e107afc29dc4b7b218383b8a09303 100644 (file)
--- a/src/actual_pinmux.py
+++ b/src/actual_pinmux.py
@@ -28,25 +28,28 @@ dictionary = {
 # second argument is the mux value.
 # Third argument is the signal from the pinmap file
 mux_wire = '''
-      rule assign_{2}_on_cell{0}(wrmux{0}=={1});
-        {2}<=cell{0}_in;
+      rule assign_{2}_on_cell{0}(wrcell{0}_mux=={1});
+        {2}<=cell{0}_mux_in;
       endrule
 '''
 dedicated_wire = '''
       rule assign_{1}_on_cell{0};
-        {1}<=cell{0}_in;
+        {1}<=cell{0}_mux_in;
       endrule
 '''
 # ============================================================
 pinmux = ''' '''
 digits = maketrans('0123456789', ' '*10) # delete space later
 
+def cn(idx):
+    return "cell%s_mux" % str(idx)
+
 for cell in muxed_cells:
-    pinmux = pinmux + "      cell" + str(cell[0]) + "_out="
+    pinmux = pinmux + "      %s_out=" % cn(cell[0])
     i = 0
     while(i < len(cell) - 1):
-        pinmux = pinmux + "wrmux" + \
-            str(cell[0]) + "==" + str(i) + "?" + cell[i + 1] + "_io:"
+        pinmux = pinmux + "wr%s" % cn(cell[0]) + \
+             "==" + str(i) + "?" + cell[i + 1] + "_io:\n\t\t\t"
         if(i + 2 == len(cell) - 1):
             pinmux = pinmux + cell[i + 2] + "_io"
             i = i + 2
@@ -82,8 +85,8 @@ for cell in muxed_cells:
 
 # ==================  Logic for dedicated pins ========= #
 for cell in dedicated_cells:
-    pinmux = pinmux + "      cell" + \
-        str(cell[0]) + "_out=" + cell[1] + "_io;\n"
+    pinmux = pinmux + "      %s" % cn(cell[0]) + \
+        "_out=" + cell[1] + "_io;\n"
     temp = cell[1].translate(digits)
     x = dictionary.get(temp)
     if(x == "input"):

diff --git a/src/interface_decl.py b/src/interface_decl.py
index 3bc5e9b8b8dc874d05206230a157f2fe586b1da6..33f66880244ad69b9321fc9f84e27bc19f1d1610 100644 (file)
--- a/src/interface_decl.py
+++ b/src/interface_decl.py
@@ -117,7 +117,7 @@ class MuxInterface(Interface):
         return "cell{0}_mux"
 
     def ifacefmtinfn(self, name):
-        return "wrmux{0}"
+        return "wrcell{0}_mux"
 
 class IOInterface(Interface):
 
@@ -125,15 +125,15 @@ class IOInterface(Interface):
     #    return "cell{0}_mux"
 
     def ifacefmtoutfn(self, name):
-        return "cell{0}_out.%s" % (name[3:-4])
+        return "cell{0}_mux_out.%s" % (name[3:-4])
 
     def ifacefmtinfn(self, name):
-        return "cell{0}_in"
+        return "cell{0}_mux_in"
 
 
 # ========= Interface declarations ================ #
 
-mux_interface = MuxInterface([{'name': 'cell{0}', 'ready':False,
+mux_interface = MuxInterface([{'name': 'cell{0}_mux', 'ready':False,
                       'enabled':False,
                      'bitspec': '{1}', 'action': True}])
 

diff --git a/src/interface_def.py b/src/interface_def.py
index 283e6c2b52bf03b7b63234c65ee7335d5045bbb5..42ce5f2c3e11d5d4c738b16c487aca08c0973de1 100644 (file)
--- a/src/interface_def.py
+++ b/src/interface_def.py
@@ -1,20 +1,20 @@
 # === templates for interface definitions ====== #
 mux_interface_def = '''
       method Action  cell{0}_mux(Bit#({1}) in);
-         wrmux{0}<=in;
+         wrcell{0}_mux<=in;
       endmethod
 '''
 io_interface_def = '''
-      method io_outputval_{0}=cell{0}_out.outputval;
-      method io_output_en_{0}=cell{0}_out.output_en;
-      method io_input_en_{0}=cell{0}_out.input_en;
-      method io_pullup_en_{0}=cell{0}_out.pullup_en;
-      method io_pulldown_en_{0}=cell{0}_out.pulldown_en;
-      method io_drivestrength_{0}=cell{0}_out.drivestrength;
-      method io_pushpull_en_{0}=cell{0}_out.pushpull_en;
-      method io_opendrain_en_{0}=cell{0}_out.opendrain_en;
+      method io_outputval_{0}=cell{0}_mux_out.outputval;
+      method io_output_en_{0}=cell{0}_mux_out.output_en;
+      method io_input_en_{0}=cell{0}_mux_out.input_en;
+      method io_pullup_en_{0}=cell{0}_mux_out.pullup_en;
+      method io_pulldown_en_{0}=cell{0}_mux_out.pulldown_en;
+      method io_drivestrength_{0}=cell{0}_mux_out.drivestrength;
+      method io_pushpull_en_{0}=cell{0}_mux_out.pushpull_en;
+      method io_opendrain_en_{0}=cell{0}_mux_out.opendrain_en;
       method Action  io_inputval_{0}(Bit#(1) in);
-         cell{0}_in<=in;
+         cell{0}_mux_in<=in;
       endmethod
 '''
 uartinterface_def = '''