class ExampleBufDelayedPipe(BufferedPipeline):
def __init__(self):
- stage = ExampleStageDelayCls(valid_trigger=3)
+ stage = ExampleStageDelayCls(valid_trigger=2)
BufferedPipeline.__init__(self, stage, stage_ctl=True,
buffermode=True)
BufferedPipeline.__init__(self, stage, buffermode=False)
+######################################################################
+# Test 16
+######################################################################
+
class ExampleBufModeUnBufPipe(ControlBase):
def elaborate(self, platform):
f.write(vl)
print ("test 15)")
- dut = ExampleBufModeUnBufPipe()
+ dut = ExampleBufModeAdd1Pipe()
data = data_chain1()
- test = Test5(dut, test9_resultfn, data=data)
+ test = Test5(dut, test12_resultfn, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
ports = [dut.p.i_valid, dut.n.i_ready,
dut.n.o_valid, dut.p.o_ready] + \
with open("test_bufunbuf15.il", "w") as f:
f.write(vl)
+ print ("test 16)")
+ dut = ExampleBufModeUnBufPipe()
+ data = data_chain1()
+ test = Test5(dut, test12_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufunbuf16.il", "w") as f:
+ f.write(vl)
+
print ("test 999 (expected to fail, which is a bug)")
dut = ExampleBufUnBufPipe()
data = data_chain1()