Separate input and output ports by color

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 489ad9edd675b5d5ba61d1aad676c5710a389b3a..e17269d64e2b3262f6f3fede41ea1a08dedfd385 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -316,25 +316,32 @@ def scoreboard_sim(dut):
 
 def test_compunit_fsm():
     top = "top.cu" if is_engine_pysim() else "cu"
+    style = {
+        'in': {'color': 'orange'},
+        'out': {'color': 'yellow'},
+    }
     traces = [
         'clk',
         ('operation port', {'color': 'red'}, [
-            'oper_i_None__sdir', 'cu_issue_i',
-            'cu_busy_o']),
-        ('operand 1 port', {'color': 'yellow'}, [
+            'cu_issue_i', 'cu_busy_o',
+            {'comment': 'operation'},
+            'oper_i_None__sdir']),
+        ('operand 1 port', 'in', [
             ('cu_rd__rel_o[1:0]', {'bit': 1}),
             ('cu_rd__go_i[1:0]', {'bit': 1}),
             'src1_i[7:0]']),
-        ('operand 2 port', {'color': 'yellow'}, [
+        ('operand 2 port', 'in', [
             ('cu_rd__rel_o[1:0]', {'bit': 0}),
             ('cu_rd__go_i[1:0]', {'bit': 0}),
             'src2_i[7:0]']),
-        ('result port', {'color': 'orange'}, [
+        ('result port', 'out', [
             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
         ('alu', {'module': top+'.alu'}, [
-            'p_data_i[7:0]', 'p_shift_i[7:0]', 'op__sdir',
-            'p_valid_i', 'p_ready_o', 'n_valid_o', 'n_ready_i',
-            'n_data_o[7:0]'
+            ('prev port', 'in', [
+                'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
+                'p_valid_i', 'p_ready_o']),
+            ('next port', 'out', [
+                'n_data_o[7:0]', 'n_valid_o', 'n_ready_i']),
         ]),
         ('debug', {'module': 'top'},
          ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])
@@ -343,7 +350,7 @@ def test_compunit_fsm():
     write_gtkw(
         "test_compunit_fsm1.gtkw",
         "test_compunit_fsm1.vcd",
-        traces,
+        traces, style,
         module=top
     )
     m = Module()