INF + -INF bug
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 19 Feb 2019 08:23:20 +0000 (08:23 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 19 Feb 2019 08:23:20 +0000 (08:23 +0000)
src/add/nmigen_add_experiment.py
src/add/test_add.py

index 26c779ff7231c0bc97112a7654d94025fd7c87d5..e1d0b40c1114da2b33144825b4951ef0fca80555 100644 (file)
@@ -66,7 +66,7 @@ class FPADD(FPBase):
                     m.d.sync += z.inf(a.s)
                     # if a is inf and signs don't match return NaN
                     with m.If((b.e == b.P128) & (a.s != b.s)):
-                        m.d.sync += z.nan(b.s)
+                        m.d.sync += z.nan(1)
 
                 # if b is inf return inf
                 with m.Elif(b.is_inf()):
index d97ade8d09858af00e9f1b5f8d3577df76014c55..bb419049f420939d8284719c7abede8d3d6b5dd9 100644 (file)
@@ -13,6 +13,9 @@ from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
                                 run_edge_cases, run_corner_cases)
 
 def testbench(dut):
+    yield from check_case(dut, 0xFF800000, 0x7F800000, 0xFFC00000)
+    #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    yield from check_case(dut, 0x7F800000, 0xFF800000, 0xFFC00000)
     yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000)
     yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000)
     yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
@@ -35,8 +38,6 @@ def testbench(dut):
     yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
     yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
     yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
-    yield from check_case(dut, 0x7F800000, 0xFF800000, 0xFFC00000)
-    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
     yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
     yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
     yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)