add clock domain using snippet taken from random file

diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py
index 1a4a2d66727c94911fffd4936ee5483d987b9b99..8707ba000b16f27a8989b08820a1bd0b9c0f2701 100644 (file)
--- a/src/soc/litex/sim.py
+++ b/src/soc/litex/sim.py
@@ -4,8 +4,11 @@
 # This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
 # License: BSD
 
+import os
 import argparse
 
+from migen import ClockDomain
+
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform
 from litex.build.sim.config import SimConfig
@@ -73,6 +76,12 @@ class SoCSMP(SoCCore):
         self.platform.name = "sim"
         self.add_constant("SIM")
 
+        self.clock_domains.cd_sys = ClockDomain()
+        self.comb += [
+            self.cd_sys.clk.eq(platform.request("sys_clk")),
+            self.cd_sys.rst.eq(platform.request("sys_rst"))
+        ]
+
         # SDRAM ----------------------------------------------------------
         phy_settings = get_sdram_phy_settings(
             memtype    = "DDR3",