convert PortInterfaceBase to pass msr not msr_pr

https://bugs.libre-soc.org/show_bug.cgi?id=756

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 0c5ac8d8f88b5f208e17693248b3198541dcd200..58f6c4e82eac7137ffa18a4b6a873c9a9a72bcf8 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -260,7 +260,7 @@ class PortInterfaceBase(Elaboratable):
             comb += lenexp.len_i.eq(pi.data_len)
             comb += lenexp.addr_i.eq(lsbaddr)
             with m.If(pi.addr.ok & adrok_l.qn):
-                self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
+                self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr)
                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 
@@ -272,7 +272,7 @@ class PortInterfaceBase(Elaboratable):
             comb += lenexp.len_i.eq(pi.data_len)
             comb += lenexp.addr_i.eq(lsbaddr)
             with m.If(pi.addr.ok):
-                self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr,
+                self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr,
                                  pi.is_dcbz_i)
                 with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok