increment CRs based on srcstep, see what happens

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index a5fde3b341455adff1bcbae6e2ecbe94a667b454..8a3591fefc8dabc143f66b4036ee712cb319da44 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -1168,7 +1168,10 @@ class PowerDecode2(PowerDecodeSubset):
             comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
             comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
             comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
-            comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
+            with m.If(svdec.isvec):
+                comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output
+            with m.Else():
+                comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
             comb += to_reg.ok.eq(fromreg.ok)
 
         # sigh this is exactly the sort of thing for which the