fix combinatorial loop in ldst compunit

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index f33237bf0624d44bdcf7f61c86319bcf1f57f0be..847f96cd01c777ed54bac54eb051a6aaf3350fcd 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -348,7 +348,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # store latch
         comb += sto_l.s.eq(addr_ok & op_is_st)
-        comb += sto_l.r.eq(reset_s | p_st_go)
+        sync += sto_l.r.eq(reset_s | p_st_go)
 
         # ld/st done.  needed to stop LD/ST from activating repeatedly
         comb += lsd_l.s.eq(issue_i)

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 4e8a7f16255841e1f2c0bef14fe8afc5c4fa3a24..d93e3782b599dc4b17c98bbdaee0b3198e016f88 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -109,7 +109,7 @@ class TestIssuer(Elaboratable):
         ldst = core.fus.fus['ldst0']
         st_go_edge = rising_edge(m, ldst.st.rel_o)
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
-        m.d.sync += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
+        m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 
         # PC and instruction from I-Memory
         current_insn = Signal(32) # current fetched instruction (note sync)