add logical pipeline to Power decode Function enum

diff --git a/libreriscv b/libreriscv
index 7ced351c57a207e733bc8c95c923cbfe91d31831..29219bd53d45768c6f57a876a78c5758b29bd7d1 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 7ced351c57a207e733bc8c95c923cbfe91d31831
+Subproject commit 29219bd53d45768c6f57a876a78c5758b29bd7d1

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 93c6b07b48cdd7a9d17010d7f8d43c73c6323f97..50a91855a33505024b0a6207a932b493fcab9155 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -39,13 +39,16 @@ def get_signal_name(name):
         name = "is_" + name
     return name.lower().replace(' ', '_')
 
-
+# this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
+# is to process and guard the operation.  they are roughly divided by having
+# the same register input/output signature (X-Form, etc.)
 @unique
 class Function(Enum):
     NONE = 0
     ALU = 1
     LDST = 2
     SHIFT_ROT = 3
+    LOGICAL = 4
 
 
 @unique